Headless KiCad with kicad-cli: automate your PCB checks
Build a headless KiCad 9 pipeline that runs ERC, DRC with schematic parity, BOM export, Gerber plotting, and drill generation with reliable CI failures.
Read article →MakeIRL engineering notes
KiCad checks, PCB manufacturing, and hardware that ships.
Concrete workflows for turning a schematic and board into fabrication files you can inspect, automate, and order with fewer surprises.
KiCad
10 articlesHow to add a ground plane (copper pour) in KiCad PCB Editor
Create and verify a KiCad ground plane with the Filled Zone tool, sensible clearance and thermal settings, zone refills, stitching vias, and island checks.
Read article →How to diagnose and fix "unconnected items" in KiCad DRC
Find and fix KiCad DRC unconnected items by tracing ratsnest lines, refilling zones, checking pad nets and numbers, and repairing nearly connected tracks.
Read article →How to export Gerbers from KiCad for a reliable JLCPCB order
Export a complete KiCad Gerber and Excellon drill archive for JLCPCB, choose the right layers, and verify the plotted board before placing an order.
Read article →How to run ERC in KiCad from the command line reliably
Run KiCad electrical rules checks with kicad-cli, produce readable or JSON reports, and make ERC failures stop a local script or CI build reliably.
Read article →KiCad 9 vs 8: what changed for day-to-day PCB designers
Compare the KiCad 9 features that changed real PCB workflows, from component classes and zone management to via tenting, pad stacks, DRC, and CLI exports.
Read article →KiCad DRC violations explained: what each one really means
Decode common KiCad DRC violations, trace each message back to its governing rule, and decide whether to reroute, change a footprint, or document an exception.
Read article →KiCad footprint vs symbol: what PCB beginners get wrong
Understand how KiCad symbols, footprints, pins, and pads relate, then choose and verify packages without creating swapped nets, holes, or unbuildable boards.
Read article →KiCad schematic parity: keeping schematic and PCB in sync
Keep KiCad schematic and PCB data synchronized, understand UUID-based linking, and run parity checks that catch missing footprints, extra parts, and net drift.
Read article →Setting up a KiCad BOM with real manufacturer part numbers
Build a KiCad BOM around exact manufacturer part numbers, supplier SKUs, footprints, and DNP status so purchasing and assembly receive usable data.
Read article →Manufacturing
10 articlesA practical PCB DFM checklist before you place an order
Use this practical PCB DFM checklist to verify fab limits, outline and drill data, copper, solder mask, silkscreen, BOM, placement, and final Gerbers.
Read article →How Much Does a Small PCB Fabrication and Assembly Run Cost?
Estimate the real cost of a small PCB run, including fabrication, shipping, components, assembly setup, yield, taxes, and costly nonstandard options.
Read article →Minimum trace width and clearance fabs actually accept
Compare PCB fab trace and spacing limits, understand standard versus advanced capability, and configure conservative KiCad constraints for a reliable order.
Read article →PCB Drill Sizes and Annular Rings Explained for Fabrication
Choose PCB drill sizes and annular rings that fit component leads, plating tolerances, and fab capabilities, then enforce them correctly in KiCad.
Read article →PCB Pick-and-Place Files (CPL/XYRS): A Practical Workflow
Understand CPL, centroid, XYRS, and pick-and-place files: required columns, origins, rotations, KiCad export steps, and assembly preview checks.
Read article →PCBA vs bare PCB: what you are actually ordering from a fab
Learn the difference between a bare PCB and PCBA order, which files and supply decisions assembly adds, and what placement, soldering, and test include.
Read article →Solder mask bridges: what they are and why they matter
Understand solder mask bridges between PCB pads, how opening expansion and fab registration set the web width, and when fine-pitch apertures should merge.
Read article →Understanding a practical PCB stackup for 2-layer boards
Understand a 2-layer PCB stackup, including copper, FR-4, mask, thickness, return paths, impedance limits, copper weight, and when four layers are safer.
Read article →What Is a Gerber File? PCB Manufacturing Data Explained
Learn what Gerber PCB files contain, why drill and assembly data are separate, and how to export and inspect a correct fabrication package from KiCad.
Read article →Why your PCB order got rejected: common fabrication issues
Learn why PCB orders fail upload or CAM review, from broken outlines and unsupported drills to capability mismatches, ambiguous layers, and bad panel data.
Read article →Sourcing
5 articlesHow to Check Electronic Part Availability Before PCB Order
Check exact MPN stock, lifecycle, lead time, assembly inventory, and alternates before PCB release, then preserve the sourcing evidence in your KiCad BOM.
Read article →LCSC vs DigiKey vs Mouser: Sourcing Parts for Small PCB Runs
Compare LCSC, DigiKey, and Mouser for low-volume PCB builds by exact-MPN stock, assembly integration, documentation, shipping, price, and sourcing risk.
Read article →MPN Matching for PCB Assembly: Why Exact Part Numbers Matter
Exact manufacturer part number matching prevents wrong packages, pinouts, tolerances, grades, and packing from reaching PCB assembly. Build a verifiable BOM.
Read article →Reading a Datasheet: 5 Things That Matter for PCB Layout
Read the five datasheet sections that control PCB layout: package and pins, external parts, critical loops, thermal design, and land-pattern mechanics.
Read article →What to Do When a PCB Component Goes Out of Stock Mid-Project
Recover from an out-of-stock PCB component without creating a hidden redesign: verify supply, qualify alternates, update KiCad, and re-release outputs.
Read article →AI & vibecoding
10 articlesAI PCB Design Tools Compared: An Engineering Guide for 2026
Compare AI PCB design tools in 2026 by their real scope: browser copilot, architecture generation, autonomous layout, enterprise routing, and EDA export.
Read article →Can AI Design a PCB? An Honest Engineering Assessment for 2026
AI can assist PCB architecture, schematic capture, sourcing, placement, and routing, but a manufacturable board still needs grounded data and verification.
Read article →Code-Native EDA: A Practical Guide to Circuit Boards as Code
Code-native EDA expresses circuits and constraints in text for Git, reuse, testing, and CI. Learn how SKiDL, atopile, tscircuit, and KiCad fit.
Read article →From Natural Language to a Real Circuit Board: The Pipeline
Turn a hardware prompt into a buildable PCB through structured requirements, grounded parts, generated EDA source, deterministic checks, and physical tests.
Read article →How to Vibecode an ESP32 Board (and What to Check)
Vibecode an ESP32 board without trusting guessed pins: define constraints, use a module reference design, verify power, boot, USB, layout, and bring-up.
Read article →MCP for Hardware: Connect Your Editor to a PCB Pipeline
Use MCP for hardware to expose KiCad checks, board metadata, and release artifacts to an editor without giving an AI unrestricted shell access.
Read article →The Limits of AI in Hardware Design: What It Cannot Do Yet
AI hardware tools cannot yet guarantee requirements, pin truth, analogue behavior, EMI, thermal safety, manufacturability, sourcing, or physical validation.
Read article →What Is Vibecoding Hardware, and Can It Actually Work Safely?
Vibecoding hardware uses natural language and coding agents to build electronics, but it works only with explicit constraints, checks, and physical testing.
Read article →Why a Manufacturing Gate Matters More Than an AI Designer
A PCB manufacturing gate independently checks ERC, DRC, parity, BOM, stock, Gerbers, drills, placement, and revision control before any board is ordered.
Read article →Why LLMs Hallucinate PCB Pin Numbers—and How to Stop It
LLMs confuse PCB pin numbers because packages, variants, and diagram views differ. Use exact MPNs, primary datasheets, pin contracts, and KiCad checks.
Read article →Modules
7 articlesAdding a Qwiic/I2C Connector to Your Board
Add a Qwiic I2C connector with the correct JST-SH pinout, 3.3 V power, calculated pull-ups, a verified footprint, bus protection, and scope tests.
Read article →Decoupling Capacitors: How Many and Where to Place Them
Choose and place PCB decoupling capacitors by power pin, transient current, package, and return path instead of copying a single 100 nF rule everywhere.
Read article →ESP32-C3 Carrier Board Design Basics
Design an ESP32-C3 module carrier with reliable 3.3 V power, boot and reset controls, USB or UART programming, safe GPIO choices, and RF clearance.
Read article →Reset and Boot Circuits for ESP32 and RP2040
Design reliable ESP32-C3 and RP2040 reset and boot circuits with correct pull resistors, buttons, timing, auto-programming controls, and recovery pads.
Read article →RP2040 Minimal Design: The Essential Circuit
Build an RP2040 minimal circuit with correct 3.3 V and 1.1 V rails, QSPI flash, clock, USB, SWD, RUN reset, BOOTSEL, and practical layout checks.
Read article →Status LEDs Done Right: Current-Limiting Resistors
Calculate a status LED resistor from voltage, forward drop, and target current; then check GPIO limits, boot behavior, polarity, PWM, and PCB placement.
Read article →USB-C Power on a Dev Board: CC Resistors and ESD
Wire a USB-C dev-board power input correctly with separate CC pull-downs, safe VBUS handling, USB 2.0 data routing, ESD protection, and cable tests.
Read article →Concepts
8 articlesCourtyard, Keepout, and Clearance: PCB Terms Decoded
Understand PCB courtyards, keepouts, and clearances in KiCad: what each boundary controls, how DRC uses it, and where manufacturing constraints differ.
Read article →ERC vs DRC: What’s the Difference in PCB Design?
Learn how electrical rule checking and design rule checking catch different schematic and PCB errors, how to run both in KiCad, and what they cannot prove.
Read article →From Breadboard to PCB: The First-Timer’s Path
Turn a working breadboard into a first PCB by capturing the schematic, choosing orderable parts and footprints, planning power, layout, checks, and bring-up.
Read article →Netlist Explained for PCB Beginners
A PCB netlist records which component pins must connect. Learn how schematic labels become board ratsnest lines, how pin mapping fails, and how to verify it.
Read article →PCB Design Mistakes That Cost You a Respin
Avoid expensive PCB respins by auditing connector views, symbol-to-footprint pins, power, boot access, mechanics, BOM variants, zone fills, and fab outputs.
Read article →Two-Layer vs Four-Layer PCB: Which Do You Need?
Choose a two-layer or four-layer PCB from routing density, return paths, EMI, impedance, power integrity, fabrication cost, and prototype risk.
Read article →What Is a Copper Pour and When Should You Use One?
A PCB copper pour is a net-assigned filled zone. Learn when to use ground or power pours, set thermal relief and clearance, avoid islands, and verify returns.
Read article →What Release for Manufacturing Means for a PCB
A PCB release for manufacturing is a controlled, reproducible artifact set: approved design revision, checks, BOM, Gerbers, drill and assembly files.
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