Decoupling Capacitors: How Many and Where to Place Them

A decoupler closes a current loop

A digital IC draws current in short edges, not only at its average datasheet value. The regulator and long power trace cannot supply every edge without voltage movement because the path has inductance. A nearby capacitor supplies the transient locally, then recharges more slowly.

The loop is:

IC power pin -> switching logic -> IC ground -> capacitor ground
             <- capacitor supply <-------+

The useful capacitor is the one that makes this loop small. A 100 nF part beside the regulator may be electrically farther away than a 10 nF part beside the IC pin. “The board has enough total capacitance” is therefore the wrong test.

Count power pins, then read the datasheet

Start by listing every supply pin and domain:

Device domain	Pins	Voltage	Datasheet requirement
MCU I/O supply	3	3.3 V	100 nF at each pin
MCU core regulator output	2	1.1 V	specified local total
ADC/reference	1	3.3 V	filtered/quiet network
Radio module input	1	3.3 V	100 nF plus local bulk

This table prevents hidden pins and distinct rails from being merged under a generic VCC label. Follow the manufacturer’s recommended count and values first. “One 100 nF per power pin” is a useful default only when the datasheet is silent; it cannot override a regulator stability requirement or a radio module’s bulk-capacitor recommendation.

Read footnotes too. Some pins must be powered even when a peripheral is unused. Some internal-regulator outputs require a particular capacitance and effective-series-resistance range. The five layout facts to extract from a datasheet helps find those conditions.

Choose real capacitors, not ideal values

Capacitance printed on the schematic is nominal. A multilayer ceramic capacitor loses effective capacitance with DC bias, especially in small packages and high-capacitance values. A 10 µF, 6.3 V, 0402 capacitor operated near its rating may provide far less than 10 µF. Check the manufacturer’s bias curves and choose voltage rating, dielectric, and package accordingly.

For general digital decoupling, 100 nF X7R in 0402 or 0603 is common. Smaller packages usually have lower connection inductance, but use a size your assembler can place reliably. Add 1–10 µF local bulk near a processor, module, connector, or load step as its reference design requires. Larger board-level bulk belongs near the power entry or regulator, not as a substitute for pin-level parts.

A radio module is a good example of local bulk serving a burst load; the ESP32-C3 carrier design shows how that capacitor fits into the complete supply path.

Mixing 100 nF, 10 nF, and 1 nF everywhere is not automatically better. Real capacitors and planes form resonances, and a poorly chosen mixture can create an impedance peak. For demanding FPGAs, fast processors, or RF systems, build a target-impedance model or follow the vendor’s power-distribution-network guidance. A modest MCU board usually benefits more from correct placement and a continuous plane than from a decorative ladder of values.

Place in pin-capacitor-via order

Place the capacitor immediately beside its power pin, ideally before routing the rest of the board. Route the supply plane or trace to the capacitor pad and then to the IC pin where practical. Put a ground via beside the capacitor’s ground pad; do not run a long ground trace to a distant via.

Good geometry looks like:

3V3 plane/via -> capacitor supply pad -> short trace -> IC VDD
IC GND/paddle -> ground plane <- nearby via <- capacitor ground pad

Avoid thermal-relief spokes on high-frequency ground connections if manufacturing rules and the plane arrangement allow a solid connection. Avoid a via shared by several capacitors through a long neck. On a QFN, rotate each capacitor so both pads reach the appropriate pin/plane without crossing.

On a two-layer board, reserve one side as continuous ground as much as possible. If a power trace forces the return current around a slot, the decoupling loop grows. A four-layer board often improves power integrity because a solid ground plane can sit directly below the signal/power layer.

Separate local decoupling from regulator stability

A regulator’s input and output capacitors are part of its control loop. Use the values, dielectric, ESR, and placement specified in the regulator datasheet. An LDO that requires minimum ESR can oscillate with a very low-ESR ceramic; another LDO may require ceramic parts. A buck converter’s input capacitor must close the high-current switch loop beside VIN and ground, while its output capacitor belongs beside the inductor/load return topology shown in the layout guide.

Do not place a ferrite bead between an IC supply pin and its only decoupler. Put the local capacitor on the IC side of the bead so high-frequency current has a short loop. For an ADC or radio rail, copy the recommended bead/inductor and capacitor arrangement and check the bead’s current rating and DC resistance.

Represent the network clearly in KiCad

Put decouplers next to the power unit of the symbol or in a dedicated “Power and decoupling” block. Name rails distinctly and annotate each capacitor. A note such as Place within 2 mm of U3 pin 17 communicates intent to the layout reviewer.

Assign footprints before placement and verify the voltage rating in BOM fields. Use KiCad’s highlight-net tool to inspect every supply pin, then switch to the ground net and look for islands or narrow necks. Refill zones before DRC. The copper pour guide explains why an unfilled or isolated ground zone cannot complete the intended return path.

Diagnose a decoupling problem

Symptoms include random resets during radio transmit, ADC noise correlated with CPU activity, USB disconnects, and an otherwise-correct regulator that rings. Measure at the IC pins with a short ground spring; a long probe ground lead can display its own ringing.

Trigger on reset or the load event and compare the rail at the regulator and at the IC. If droop exists only at the load, inspect trace/plane impedance and local capacitance. If both locations droop, review regulator response, input source, and bulk capacitance. Populate reserved capacitor footprints one change at a time and record the waveform. That turns “add more caps” into an engineering result that can be carried into the next revision.