makeIRLEarly access

PCB release gate

Automated PCB design checks.
Then real fabrication.

Today: bring your own KiCad project — hand-drawn, or vibecoded through Claude Code or Cursor. Our release gate runs ERC, DRC, schematic-parity, and BOM-stock checks before a real factory builds and ships the board. Natural-language generation is next.

No spam. One email when the release gate opens.

MakeIRL sample release — PV-2026-0001U1RP2040J1USB-CC1C2R1R2J2 · QWIIC3V3SDAGNDSCLMAKEIRLPV-2026-0001 · REV A86.0 mm61.0 mm

Process

Three steps from file to shipment

  1. 01

    Bring or vibecode your design

    Drop in a .kicad_pcb / .kicad_sch project — hand-drawn in KiCad, or generated through Claude Code or Cursor over MCP. The gate doesn't care how it was made.

  2. 02

    The release gate checks it

    ERC, DRC, schematic-parity, and live BOM-stock checks run deterministically. Every finding shows its receipts: the tool, the version, the exact location on the board.

  3. 03

    A real factory builds it

    Pass the gate, place one order, and a real contract manufacturer builds and ships the physical board to your door.

Why preflight · updated July 2026

Respins are expensive. Catching them early isn’t.

PCB designs average 2.9 respins from insufficient analysis. Each respin costs an average of $28,482 and takes 16 days — getting the board right the first time saves an average of 36 days and $82,600.

Source: Siemens Digital Industries Software, citing Aberdeen Group research, 2020

“Find the errors early and they’re cheaper to fix.”

From your editor

Run the release gate without leaving your terminal

MakeIRL ships as an MCP server. Point Claude Code or Cursor at it and preflight a board the same way you'd run a test suite.

Illustrative session. The release gate is real; natural-language board generation is not shipped yet.

claude code
$ claude mcp add makeirl https://mcp.makeirl.com/v1
 
> preflight_start(files: "./board")
  { job_id: "pf_8a2f1c" }
 
> preflight_status(job_id: "pf_8a2f1c")
  ERC · DRC · schematic parity · BOM stock — running…
 
> get_report(job_id: "pf_8a2f1c")
  4 / 5 checks passed · 1 warning
  report: makeirl.com/r/8a2f1c

Live on every run

Checks stamp in, one by one

No spinner. Each check runs, resolves, and stamps — the same way you'd watch a CI pipeline pass.

release-gate · run pf_8a2f1c0 / 5 passed
  • ERC…
  • DRC…
  • Schematic parity…
  • BOM stock…
  • DFM…

Scope, stated plainly

What we check. What we can’t.

A release gate catches the mistakes that kill a first board run. It can’t promise your design does what you meant — nothing automated can, and every report you get says so explicitly.

What we check

  • Electrical rule violations (ERC)
  • Manufacturing clearances (DRC)
  • Schematic ↔ PCB parity
  • BOM line availability against live stock
  • Footprint / package sanity

What we can’t check

  • Whether your design does what you meant it to do
  • Firmware or embedded code correctness
  • RF, EMC, or thermal performance
  • Mechanical fit inside an enclosure
  • High-speed signal-integrity margins

Early access

Get notified when the release gate opens

We’ll email once, when you can run your first board through it.