Why your PCB order got rejected: common fabrication issues

Rejected can mean three different things

A board can stop at the uploader, at automated design-for-manufacture analysis, or during human CAM review. The distinction points to the fix:

• Upload or parsing failure: the service could not identify a valid board set in the archive.
• Capability or quote mismatch: it understood the geometry, but the data exceeds the options you selected.
• Engineering question or hold: the CAM engineer found ambiguity that requires confirmation or corrected files.

A hold is not always evidence of a bad design. It can be the fab refusing to guess whether a line is a slot, whether a hole is plated, or which of two outlines is real. Resolve that ambiguity in the source and release package instead of answering “make as-is” without understanding the consequence.

The outline is missing, open, or ambiguous

Fabricators need a closed route path for the board perimeter and each internal cutout. Common outline problems include:

• no Edge.Cuts Gerber in the archive;
• a microscopic gap between lines or arcs;
• overlapping or duplicated segments;
• self-intersecting geometry;
• a drawing frame plotted on the outline layer;
• two different perimeter candidates on separate mechanical layers;
• V-score lines or routed slots not identified clearly.

KiCad DRC reports malformed outlines, but still inspect the exported Gerber. Use one closed contour for the exterior and closed contours for routed cutouts. Put dimensions and explanatory text in a fabrication drawing, not on top of the machine route unless the fab documents that convention.

The archive does not match the selected layer count

Selecting “2 layers” while uploading four copper Gerbers creates an obvious mismatch. More subtle cases include an empty inner layer, an inner plane plotted twice, or custom copper layer names that the uploader maps incorrectly.

Count the copper layers in a local Gerber viewer and assign them explicitly in the online preview. For multilayer boards, confirm the sequence and stackup; swapping In1.Cu and In2.Cu can alter plane relationships and impedance even though the layer count is correct.

Remove unrelated plots. Courtyards, fabrication outlines, drill maps, PDFs, and old Gerbers from another revision can confuse automatic classification when mixed into the same zip. The KiCad-to-JLCPCB Gerber guide lists a clean normal layer set.

Drills and slots exceed the chosen process

A CAM hold can result from a mechanical drill smaller than the standard minimum, insufficient annular ring, too many drill types, an unsupported aspect ratio, or a slot narrower than the available router. A long slot represented as a row of overlapping drill hits may be flagged or manufactured poorly; use an actual oval drill or routed slot representation supported by the fab.

Plating status also matters. Mounting holes intended as NPTH can become plated when their copper pads or drill output say otherwise. Conversely, a connector shield tab may need plating but appear in the non-plated file. Review the PTH and NPTH drill files together with copper.

If the fab proposes enlarging a hole, check the remaining annular ring and component fit. If it proposes reducing a hole, check maximum lead tolerance. A quick approval can turn a CAM convenience into an assembly failure.

Copper geometry exceeds capability

Typical capability triggers are:

• a trace or gap below the selected tier’s limit;
• insufficient copper-to-edge or copper-to-slot distance;
• annular ring too small for drill tolerance;
• a via drill or diameter unsupported at the board thickness;
• narrow thermal spokes or zone necks;
• heavy copper combined with spacing meant for thin copper;
• fine features spread across too much of the board for a localized advanced process.

The smallest object may be inside a footprint or zone, not a routed track. Measure fine-pitch pad gaps, copper text, custom graphics, and thermal connections in the actual Gerbers. Configure KiCad constraints using the real trace and clearance capability workflow, then rerun DRC and regenerate the whole set.

Never solve a capability warning by changing the quote form to a smaller minimum than the files contain. The form describes the data; it does not resize it.

Solder mask cannot be registered as drawn

Very small solder-mask webs between fine-pitch pads may be below the process or colour-specific minimum. The fab may ask permission to remove those webs and merge the openings. It may also flag mask openings that expose nearby traces, mask slivers that will not adhere, or a missing mask layer.

Decide whether a merged opening is acceptable for assembly. For a tight-pitch IC it can be standard, but it increases dependence on paste design and process control. Do not ask the fab to preserve a mask dam it says it cannot register reliably. Update the footprint or select an appropriate mask process, then inspect the new mask Gerber.

Silkscreen over exposed pads is usually clipped automatically, but extensive collisions or unreadably small text can still generate a note. Plot clean legend data rather than relying on the CAM operator to decide which markings matter.

Board options and Gerbers disagree

The order form is part of the manufacturing specification. Rejections occur when files imply features not selected, such as:

• castellated holes at the board edge;
• edge plating or gold fingers;
• controlled impedance without a compatible stackup;
• countersinks, counterbores, depth routing, or blind/buried vias;
• via filling, capping, or tenting requirements;
• carbon ink, peelable mask, or hard-gold contacts;
• individual boards uploaded as a customer panel without panel-service options.

Choose the documented option and provide the required drawing. A note in the filename is not a substitute. If a feature is unnecessary, remove it from the design rather than asking CAM to ignore visible geometry.

Assembly data creates its own rejection class

For PCBA, a bare board can pass while the assembly order fails. Frequent causes include references in the BOM that are absent from the placement file, mismatched quantities, missing MPNs, ambiguous DNP status, coordinates outside the outline, and rotations that do not match the assembler’s convention.

Part substitutions can also trigger a hold when the selected stock code does not match the footprint or the part is unavailable. Review BOM, centroid, Gerbers, and assembly drawing as one revision-matched package.

Respond with a corrected release, not a patchwork

Ask the reviewer to identify the exact layer, coordinates, measured value, and applicable capability. Reproduce it locally. Correct the KiCad source, rerun ERC/DRC, and regenerate all outputs into an empty directory. Do not edit a Gerber by hand or replace one file in an old zip without repeating the complete review.

Before resubmitting, follow the PCB DFM checklist, inspect the archive locally, and inspect the new online preview. Record the question and resolution with the source revision. The goal is not merely to get the uploader to accept a zip; it is to make the approved data unambiguous enough that the fabricated board matches the design.