A practical PCB DFM checklist before you place an order

Freeze the order assumptions first

Design for manufacturability is a comparison between board data and a specific process. “DRC passes” is not enough if the rules describe a different layer count, copper weight, drill limit, or solder-mask process than the order form.

Write down the intended build before final review:

• fabricator and service tier;
• board dimensions and quantity;
• layer count and stackup;
• finished thickness and copper weight;
• material or Tg requirement;
• surface finish and solder-mask colour;
• minimum track, gap, drill, annular ring, and edge clearance;
• controlled impedance, castellations, edge plating, via filling, or other special processes;
• bare board, stencil, or assembled PCBA.

Use the manufacturer’s current capability table. Minimum values often depend on copper thickness, layer, board thickness, colour, and paid options. The guide to trace width and clearance that fabs accept explains why a headline minimum is not a universal design rule.

Check the source design

Before generating outputs:

• Run schematic ERC and resolve or document every exclusion.
• Update PCB from schematic and review the proposed changes.
• Refill all copper zones.
• Run PCB DRC with schematic parity using rules based on the selected process.
• Confirm every routed net is connected and no unexpected board-only footprint remains.
• Check that fitted symbols have exact MPNs and footprints.

Review the design visually as well. Inspect polarity, pin one, connector orientation, test-point access, programming headers, reset and boot straps, mounting-hole clearances, and component height. A reversed connector can satisfy every clearance rule.

Validate outline and mechanical data

The board outline on Edge.Cuts should be closed, non-self-intersecting, and free of duplicate or microscopic segments. Verify overall dimensions and internal cutouts with KiCad’s measurement tools. Distinguish routed slots from drilled holes and confirm the manufacturer supports the requested slot width.

Check:

• copper-to-edge distance, including around internal cutouts;
• components and courtyards relative to the edge;
• connector overhang and mating clearance;
• mounting-hole finished size, plating status, and hardware keepout;
• panel tabs or V-cuts only if you—not the fab—are defining the panel;
• dimensions and tolerances on a separate fabrication drawing when they matter.

Do not place ambiguous instructions on a random Gerber layer. If a note changes how the board must be routed, plated, or scored, include a clear readme or drawing and select the matching order option.

Review drills, pads, and copper

For every through-hole family, compare finished-hole size with the largest lead or hardware tolerance. Then verify the annular ring remains large enough after drill tolerance. Check plated and non-plated holes are classified correctly.

Inspect copper for:

• trace widths and gaps at or above the declared rules;
• sufficient width for current and temperature rise, not just fabrication;
• high-voltage clearance and creepage appropriate to the application;
• intact return paths beneath fast signals;
• no isolated zone islands or narrow copper slivers;
• sensible thermal relief on plane-connected pads;
• teardrops or other features only where deliberately configured;
• via aspect ratio and drill diameter within the chosen process.

If a trace necks down briefly between pads, DRC should check that local segment too. A net-class routing width is not automatically an enforced minimum in KiCad; configure board constraints or custom rules.

Inspect solder mask, paste, and silkscreen

View F.Mask and B.Mask as openings: shapes on these layers remove mask and expose copper. Confirm pads are exposed, tented vias behave as ordered, and adjacent fine-pitch pads have either a manufacturable mask web or an intentionally combined opening.

Check that mask expansion does not uncover nearby tracks. Mask colour can change achievable registration and web width, so verify the colour-specific capability. The solder-mask article on why mask bridges matter covers fine-pitch decisions.

For assembly, inspect paste apertures—especially exposed thermal pads, which normally need segmented paste rather than one large opening. Confirm DNP components are treated consistently in paste and assembly data according to the assembler’s process.

Silkscreen should not overlap exposed pads or routed edges. Make reference designators, pin-one marks, polarity symbols, connector labels, and board revision readable at manufactured line width. Do not rely on silkscreen alone for a safety-critical orientation; copper or assembly documentation may be more durable.

Check assembly data as a matched set

If ordering PCBA, the BOM needs exact MPNs, quantities, references, DNP state, and approved substitutions. The pick-and-place file needs every fitted surface-mount reference, X/Y position, board side, and rotation. Use a consistent origin and verify several asymmetric components in the assembler’s preview.

Also review:

• fiducials and tooling requirements;
• component-to-component courtyard and rework space;
• board-edge clearance for conveyors;
• polarity and pin-one information in assembly drawings;
• parts that require hand assembly, special handling, or post-wash treatment;
• connectors or tall parts that must be fitted in a sequence.

A BOM and placement file from different commits can look individually valid and still be unusable together. Generate all release artifacts from one clean source revision.

Inspect final manufacturing files independently

Generate Gerbers and Excellon drills into an empty output directory. The KiCad Gerber export workflow lists the normal two-layer set and CLI commands.

Open the generated files in a Gerber viewer and check:

1. Every expected copper, mask, silkscreen, and outline layer appears once.
2. The outline has the expected size and cutouts.
3. Drills align with pads, and PTH/NPTH separation is sensible.
4. Bottom layers are not pre-mirrored incorrectly.
5. Zone fills and thermal spokes are present.
6. Mask and silkscreen match the source intent.
7. No worksheet frame, courtyard, or stale plot entered the set.

Then upload the zip and repeat the review in the fabricator’s viewer. Compare detected dimensions, layer count, and drills with the quote. A mismatch here is a reason to stop, not a harmless preview quirk.

Release, do not merely upload

Name the archive with the board and revision. Record the source commit, KiCad version, DRC/ERC reports, BOM revision, and order configuration. Hash or preserve the exact uploaded archive. If anything changes—even a reference label—regenerate and re-review the complete set rather than replacing one file inside the zip.

The common PCB rejection reasons are mostly disagreements between data, capability, and order options. This checklist makes those three explicit before money and schedule are attached to the board.