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KiCad

How to export Gerbers from KiCad for a reliable JLCPCB order

Export a complete KiCad Gerber and Excellon drill archive for JLCPCB, choose the right layers, and verify the plotted board before placing an order.

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Start from a release-ready board

Gerbers are plots of the board’s manufacturing layers. They do not carry your design intent, schematic, or a magic instruction to fix omissions. If Edge.Cuts has a gap, a zone is stale, or a drill is missing, the exported archive faithfully preserves the mistake.

Before plotting:

  1. Open the PCB Editor and press B to refill all copper zones.
  2. Run Inspect → Design Rules Checker and resolve the release-blocking findings.
  3. Confirm the board outline is a closed contour on Edge.Cuts.
  4. Check the layer count, board thickness, copper weight, and any controlled-impedance assumptions against the order you intend to place.
  5. Save the board so its plot settings and filled zones are current.

The broader PCB DFM checklist catches mechanical, drill, mask, and assembly details that DRC alone cannot prove.

Select the fabrication layers in KiCad

Open File → Fabrication Outputs → Gerbers (.gbr) in the PCB Editor. Choose a dedicated output directory such as fab/gerbers/; mixing plots with source files makes it too easy to zip an old or unrelated file.

For a normal two-layer bare board, plot:

  • F.Cu and B.Cu — top and bottom copper;
  • F.Mask and B.Mask — solder mask openings;
  • F.Silkscreen and B.Silkscreen — include each side you actually use;
  • Edge.Cuts — the routed board perimeter and internal cutouts.

KiCad’s layer is named F.Silkscreen in current interfaces and CLI syntax, even though generated filenames may abbreviate it. For a four-layer board, also include every configured inner copper layer (In1.Cu, In2.Cu, and so on). Never infer layer order from filenames at upload time; make the order in KiCad match the stackup selected in the JLCPCB quote.

F.Paste and B.Paste describe stencil apertures, not bare-board copper. Include the used paste sides when the archive is also supporting a stencil or assembly order. They are not required to fabricate an unassembled PCB.

Do not plot F.Fab, B.Fab, courtyard, user drawing, or drawing-sheet layers into the bare-board archive unless JLCPCB has requested a separate mechanical document. Unexpected layers can be misclassified by an automated uploader.

Use predictable Gerber options

Extended Gerber output with embedded apertures is the normal choice. Protel-style extensions such as .GTL, .GBL, .GTS, and .GTO make automatic layer recognition easier, although the geometry—not the extension—is authoritative.

Useful plot settings are:

  • enable the check for out-of-date zone fills;
  • use the same coordinate origin for Gerbers and drills;
  • subtract solder mask from silkscreen so legend ink is not intentionally placed over exposed pads;
  • omit the worksheet or drawing-sheet frame;
  • keep the board’s saved plot settings under version control.

Reference designators and values affect silkscreen only. Plot the references if they help assembly and debugging, but inspect for clipped or overlapping text. Values are often too dense for a small board and are not needed for fabrication.

Click Plot. Then, from the same dialog, click Generate Drill Files….

Generate matching Excellon drill files

Use Excellon for the drill format, millimetres with decimal coordinates, and the absolute origin unless a documented manufacturing flow requires a different origin. Gerbers and drills must share that origin or the holes will be displaced from the pads.

Separating plated through holes (PTH) and non-plated through holes (NPTH) is unambiguous and widely accepted. It is especially useful when a footprint contains tooling or mounting holes that must remain unplated. A drill map is optional for machine input but valuable for your own review.

Generate the files into the same dedicated output directory as the Gerbers. A typical two-layer set resembles:

controller-F_Cu.gtl
controller-B_Cu.gbl
controller-F_Mask.gts
controller-B_Mask.gbs
controller-F_Silkscreen.gto
controller-B_Silkscreen.gbo
controller-Edge_Cuts.gm1
controller-PTH.drl
controller-NPTH.drl
controller-job.gbrjob

Exact names vary with KiCad settings. What matters is that every required physical layer is present exactly once and the drill data aligns.

Inspect the exported files, not just the PCB editor

Open the generated set in KiCad Gerber Viewer or another independent viewer. This is the first time you are reviewing what the factory will consume rather than the editable source.

Check all layers together and individually:

  • the outline is present, closed, and has the expected dimensions;
  • copper, mask, and silkscreen have the same origin;
  • every through-hole pad has a drill in its centre;
  • NPTH mounting holes and slots appear and are classified correctly;
  • bottom layers are not accidentally pre-mirrored;
  • solder mask openings expose pads without uncovering nearby traces;
  • silkscreen does not cover pads, holes, or critical polarity marks;
  • copper zones are filled and do not contain surprising islands.

Upload the zip to JLCPCB and repeat the inspection in its online Gerber viewer. Confirm the detected dimensions, layer count, drill count, and layer assignments before choosing order options. If the preview differs from your local viewer, stop and diagnose it; do not assume a human reviewer will reconstruct your intent. The article on common PCB order rejections covers the outline, slot, and capability mismatches most likely to trigger a question.

Export the same set with kicad-cli

For a repeatable release, save the working plot configuration in the board file and ask KiCad 9 to use it:

mkdir -p fab/gerbers

kicad-cli pcb export gerbers \
  --output fab/gerbers \
  --board-plot-params \
  hardware/controller.kicad_pcb

kicad-cli pcb export drill \
  --output fab/gerbers \
  --format excellon \
  --drill-origin absolute \
  --excellon-units mm \
  --excellon-zeros-format decimal \
  --excellon-separate-th \
  hardware/controller.kicad_pcb

pcb export gerbers is the plural command that creates one file per selected layer; pcb export gerber is a different command that combines layers into one file and is normally wrong for board fabrication. Run the commands from the project directory, keep the KiCad version pinned, and inspect the output after any plot-setting change. The headless kicad-cli workflow shows how to place DRC before export so a failed check cannot produce an apparently official release archive.

Zip only the reviewed contents of the Gerber directory. Give the archive a revision-specific name, record the matching source commit, and regenerate rather than hand-editing fabrication files.