PCB Design Mistakes That Cost You a Respin

The expensive errors are often internally consistent

ERC and DRC catch many mistakes, but the most painful respins often obey every encoded rule. A mirrored connector can match its symbol. A regulator can be routed perfectly while using the wrong fixed-voltage suffix. A board outline can be manufacturable and still miss the enclosure by 1 mm.

Preventing respins means checking the interfaces between models: datasheet to symbol, symbol to footprint, schematic to PCB, PCB to mechanics, BOM to purchasable part, and source to fabrication output.

Connector and footprint views are reversed

Connector drawings may show mating face, wire side, bottom view, or PCB view. Copying left-to-right pin order without noting the view produces a mirrored cable interface. USB-C and fine-pitch board connectors add duplicate pins, shell tabs, and multiple pad rows.

For every connector:

1. Write down the drawing’s view convention.
2. Audit datasheet pin number to symbol pin to footprint pad.
3. Print the footprint at 1:1 and place the physical part on it.
4. Check the mating cable’s pinout separately.
5. Mark pin 1 and function on assembly/silkscreen where possible.

Do the same for switches. A four-lead tactile switch usually has two internally common pairs; rotating it 90 degrees can make the button permanently short or do nothing.

The exact part suffix changes the circuit

Ordering “the same regulator” in a different suffix can change output voltage, pinout, enable polarity, package, or reel orientation. MOSFET suffixes can change footprint and maximum rating. A sensor family may contain address or interface variants.

Use exact manufacturer part numbers in the design and assembly BOM. Validate package and electrical variant against the datasheet, then match the distributor listing to that MPN. The MPN matching guide explains why a fuzzy description is not enough for PCBA.

Lock alternates by technical attributes, not “similar part.” An approved substitute should have verified pinout, package, ratings, startup behavior, and firmware identity.

Power works at idle and fails during a transient

A multimeter showing 3.3 V does not prove a radio, motor, or processor rail is stable. Common causes are an underrated source, wrong regulator capacitors, ceramic-capacitance derating, long narrow supply paths, poor ground return, and decouplers placed far from pins.

Create a power tree with worst-case current and startup/inrush. Check regulator input range, dropout, thermal dissipation, reverse current, and stability requirements. Place local decoupling by pin and bulk capacitance by load. On prototypes, scope the rail at the load during its largest event.

Also check power sequencing and back-power paths through USB, programmers, and signal pins. Two 5 V sources tied together can damage a host or make the board appear to work only while a debugger is attached.

Boot and programming access are missing

A custom board needs a recovery path that does not depend on application firmware. Typical failures include an ESP32 strap pulled to the wrong level by an LED, an RP2040 BOOTSEL button directly shorting flash chip select, swapped UART TX/RX, no common ground on the programming header, and inaccessible SWD pads.

Simulate the unpowered, reset, normal boot, and download states. Expose reset, boot, ground, voltage reference, and debug signals on labeled pads. Test the fixture orientation. A few square millimeters of test access can save an entire assembled lot.

Schematic and PCB revisions diverge

A last-minute schematic fix does not automatically change an already routed PCB unless it is transferred and reviewed. Conversely, a board-only net edit can be overwritten during the next update.

After each accepted schematic change:

save schematic -> ERC -> update PCB -> inspect change list
-> refill zones -> DRC with parity -> review affected layout

Follow the full schematic parity check. Release from a clean source commit, not a mixture of saved and unsaved editor state.

Mechanics are checked with incomplete models

Mounting holes can be the wrong size, connectors can face an enclosure wall, and a correct courtyard can omit cable bend space. 3D models may have a wrong origin, approximate body, or no mating half.

Use controlled dimensions for outline, holes, and connector locations. Overlay enclosure geometry, board-to-board mates, fasteners, light pipes, batteries, and antennas. Inspect both sides and the full insertion/removal path. Define explicit courtyard, keepout, and clearance constraints instead of relying on visual memory.

Print a 1:1 board drawing and fit major real parts. For tightly constrained products, order a mechanical sample or inexpensive unpopulated board before the full assembly run.

Zones and high-current paths hide bottlenecks

A broad copper pour can narrow between pads to a tiny neck. A high-current pad can connect through thin thermal spokes. A ground island may look filled but have no via to the main ground.

Refill zones, highlight the net, and trace the entire current path at high zoom. Count and size vias across layers. Remove floating islands and inspect return paths under fast signals. Run DRC after refill, not only before it.

Use calculations for current and temperature. Fabrication minimum width answers “can it be etched?” rather than “can it carry this load continuously?”

Fabrication exports differ from the PCB view

Wrong layer selection, missing drill files, stale zone fill, duplicate outlines, incorrect auxiliary origin, and accidental bottom mirroring can all enter the ZIP after design review. The factory builds outputs, not your intent.

Generate into an empty revision folder. Open Gerber and Excellon files in an independent viewer and check layer count, outline dimensions, slots, drills, mask, silkscreen, and polarity. For PCBA, cross-check BOM, DNP state, centroid coordinates, side, and rotation against assembly drawings.

Run the DFM checklist before ordering using the selected supplier’s actual rules.

Use a release table, not memory

Assign an owner and evidence to each risk:

Risk	Required evidence
Pin mapping	Datasheet-symbol-footprint audit
Power	Budget, thermal check, transient measurement/analysis
Boot/debug	Recovery test on first article
Mechanics	Dimensioned overlay and mating review
BOM	Exact MPN and approved alternate check
Connectivity	ERC, DRC, parity, critical-net highlight
Outputs	Independent Gerber/drill/CPL inspection

Record exclusions and open questions. A check box without a linked report, measurement, or reviewer is easy to satisfy accidentally.

For the first assembled unit, current-limit power, inspect rails, and bring up one subsystem at a time before building the rest of the lot. If a bodge is required, update the design source immediately and decide whether the fix is robust enough for the intended quantity. Respins cannot be eliminated, but the predictable ones can be caught while they still cost minutes instead of boards.