Netlist Explained for PCB Beginners

A netlist is the circuit’s connection map

A net is a group of pins that must be electrically connected. A netlist is the collection of those groups, usually along with component and pin identifiers. It turns the schematic’s lines and labels into data the PCB editor can use.

A tiny board might reduce to:

Net +3V3:
  U1 pin 17 (VDD)
  C1 pin 1
  R1 pin 1
  J1 pin 2

Net I2C_SDA:
  U1 pin 8 (GPIO6)
  R1 pin 2
  J2 pin 3 (SDA)

Net GND:
  U1 exposed pad 33
  C1 pin 2
  J1 pin 1

The netlist says nothing about the route between those pins. It does not choose track width, layer, via positions, connector orientation, or a return-current path. Those are physical PCB decisions.

Modern KiCad normally transfers connectivity directly from Schematic Editor to PCB Editor rather than asking you to export and import a standalone netlist file. The concept remains the same: symbols and wires define nets; footprints and pads implement them.

Wires, labels, and junctions create nets

In a schematic, pins joined by a continuous wire belong to one net. A junction dot makes an intentional branch. Labels connect separated wire segments with the same name, which keeps large schematics readable. Power symbols such as GND and +3V3 also act like named global connections.

This creates several beginner traps:

• Two wires that cross without a junction may remain separate.
• Two labels that look similar—SDA and SDA_—are different nets.
• Reusing a global label can join distant sheets unexpectedly.
• A wire ending one grid step before a pin can look connected while it is not.
• A ground-like symbol from a different domain may create a separate net.

Use net highlighting in Schematic Editor. Click a critical net and verify every intended pin highlights, while unrelated pins do not. Run ERC to catch unconnected pins and incompatible pin types; the command-line ERC guide makes that check repeatable.

Symbol pin numbers must match footprint pad numbers

Connectivity crosses from schematic to PCB through numbers. If symbol pin 3 is named SDA, KiCad connects that net to footprint pad 3. It does not inspect a datasheet and notice that physical pad 3 is actually SCL.

This is why a beautiful schematic and fully routed PCB can both be wrong. For every custom or uncertain library part, make a pin audit:

Datasheet pin/pad	Function	Symbol pin	Footprint pad
1	GND	1	1
2	3V3	2	2
3	SDA	3	3
4	SCL	4	4

Check the package drawing’s view convention and pin-one mark. Multi-unit symbols, exposed pads, duplicated ground pins, and connectors viewed from the mating side deserve extra care. Read KiCad footprint vs symbol for the complete mapping workflow.

The ratsnest is an unrouted view of the netlist

After Tools → Update PCB from Schematic, KiCad places new footprints and draws thin ratsnest lines between pads on each net. These lines are not copper. They are reminders of required connections that the layout has not yet satisfied.

As tracks are routed or zones connect pads, ratsnest lines disappear. If a line remains, the board still has an unconnected item—even when two pads look close. A filled ground zone may remove many GND ratsnest lines at once, but only if the zone is assigned to the correct net and actually reaches the pads.

Do not route solely to make the line count reach zero. The ratsnest does not tell you a preferred path, return plane, current requirement, differential-pair geometry, or sensitive-node isolation. It expresses connectivity, not layout intent.

When a connection will intentionally be made off-board, model the cable or connector in the schematic. When a PCB trace is intentionally absent because the connection occurs inside a component, verify the symbol/footprint pad structure. Do not hide unexplained lines; use the diagnostic process in fixing unconnected items in KiCad.

Updating the PCB is a controlled change

When the schematic changes, save it, annotate as required, assign footprints, and run Update PCB from Schematic. Read the update dialog instead of accepting it blindly. It may add/delete nets, move footprints into the placement area, or update pad connections.

Then inspect:

1. Newly added footprints and changed reference designators.
2. Critical nets with highlight-net in PCB Editor.
3. The unrouted-item count.
4. DRC with schematic parity enabled.

A PCB can otherwise preserve an older connection model. The schematic parity workflow explains how to prevent a last-minute schematic correction from missing the manufacturing files.

Use stable reference designators once BOM and assembly data exist. Re-annotating an entire board can make review difficult because R17 in the old build becomes R6 in the new one even if the physical resistor did not change.

A net name is useful engineering documentation

Unnamed nets receive generated identifiers, which are valid but harder to review. Name interfaces and important rails by function:

USB_DP
USB_DM
I2C_SCL
I2C_SDA
RESET_N
MOTOR_12V
+3V3_A
+3V3_D

The _N suffix communicates active-low behavior. Separate analog and digital rail names prevent accidental merging; connect them through the intentional bead, resistor, or net tie in the schematic. Avoid names tied only to a microcontroller pin, such as GPIO7, when SENSOR_INT_N explains the circuit’s purpose.

Net classes can then group nets that share physical rules: power tracks, USB differential pairs, high-voltage spacing, or ordinary signals. Assigning a class does not change connectivity, but it lets DRC enforce the layout requirements associated with that netlist.

Do not confuse design and manufacturing netlists

Fabricators may request an IPC-D-356 netlist for bare-board electrical test. That file describes expected connectivity in manufacturing terms and can be compared with generated copper to detect opens and shorts. It is related to, but not a replacement for, the design connectivity transferred from the schematic.

Before release, verify three views agree: the schematic’s highlighted critical nets, the PCB pads/tracks/zones, and the fabrication viewer or manufacturing netlist. A netlist is simple—pins grouped by connection—but it is the contract joining logical design to physical copper. If the numbers or names in that contract are wrong, routing skill cannot rescue the board.