USB-C Power on a Dev Board: CC Resistors and ESD

Define the port role first

The common dev-board USB-C port is a power sink and, optionally, a USB 2.0 device. It accepts 5 V on VBUS, never sources VBUS, does not negotiate USB Power Delivery, and does not implement SuperSpeed. That limited role can be built with passive Configuration Channel resistors.

If the board must source power, swap roles, request more than 5 V, or determine advertised Type-C current, use a suitable Type-C/PD controller and follow its reference design. Two resistors are not a general-purpose USB-C power controller.

Put one 5.1 kΩ pull-down on each CC pin

A sink advertises itself by presenting Rd to ground on both CC pins. For the passive sink above, connect:

CC1 -> 5.1 kΩ, 1% -> GND
CC2 -> 5.1 kΩ, 1% -> GND

These are two separate resistors. Do not short CC1 and CC2 together, and do not fit only one. The cable orientation determines which CC conductor is active; omitting the second pull-down produces a board that works in one plug orientation or with some A-to-C cables but fails with compliant C-to-C sources.

The source places Rp on its CC pins, detects your Rd, and then enables VBUS. A USB-C connector alone does not guarantee 3 A. A simple board that does not measure CC current advertisement must keep its load within the current permitted by the source and applicable USB rules. Size the local regulator for the board’s transients, but do not confuse regulator rating with permission to draw that current from every host.

Connect every duplicated receptacle pin intentionally

For a USB 2.0 Type-C receptacle:

• Join all VBUS contacts into the protected 5 V input net.
• Join all ground contacts to board ground with a low-impedance path.
• Join receptacle A6 and B6 as USB D+.
• Join receptacle A7 and B7 as USB D−.
• Leave SBU1 and SBU2 unconnected when no alternate mode uses them.
• Handle the shield with the product’s chassis/EMC strategy rather than assuming it is an ordinary signal pin.

Join each pair of duplicate USB 2.0 data contacts close to the receptacle so the unused orientation does not create a long stub. Then route one D+/D− pair to the MCU or USB transceiver. Check the connector manufacturer’s actual pin labels: some low-cost “USB-C” receptacles expose only USB 2.0 contacts, while others have every contact and a much finer footprint.

Footprint orientation is a first-order risk. Compare the recommended land pattern, mating view, PCB view, and KiCad footprint pad numbers. Print the footprint at 1:1 and place a physical connector on it before ordering boards. This catches mirrored rows and shell-tab mismatches that neither ERC nor DRC understands.

Protect VBUS as a power input

A robust power-only path is usually:

USB-C VBUS -> TVS as required -> fuse/load switch -> 5V_USB
                                         |
                                         +-> regulator -> 3V3

The exact order depends on the protection devices and grounding strategy. Choose a fuse or current-limited switch for connector, trace, and fault-current limits. Prevent reverse current if the board can also be powered from a battery, debug header, or external 5 V rail. Never tie two nominal 5 V sources directly together unless both are designed for it.

Choose a VBUS TVS with a working standoff above normal VBUS and a clamp level compatible with downstream parts. A circuit designed only for 5 V without PD should not be exposed to negotiated higher voltages. Place input bulk capacitance within USB inrush requirements; “add the largest capacitor available” can cause connection problems. The regulator’s required local input/output capacitors still apply, as explained in decoupling capacitor placement.

Use the right ESD device on data and CC

External connectors are ESD entry points. Put a low-capacitance USB data-line protection array close to the receptacle, with the shortest practical path from the protected pins to the ground return. A generic high-capacitance power TVS can distort full-speed data; select a part whose datasheet explicitly supports the intended USB data rate and voltage.

Protection selection has at least five checks:

1. Reverse standoff voltage exceeds the signal’s normal range.
2. Clamp performance is specified at a relevant surge current.
3. I/O capacitance suits USB full speed or the actual data rate.
4. Pinout and flow-through footprint match the routing.
5. The ground connection is short and has nearby vias.

Depending on product risk and compliance goals, protect CC1, CC2, and VBUS with devices intended for those lines too. Keep the unprotected trace segment between connector and protector short. ESD current follows geometry; a protector placed across the board cannot compensate for a long inductive return.

Route USB 2.0 as a pair

Use the fabricator’s actual layer stackup to choose trace width and spacing for roughly 90 Ω differential impedance. Route D+ and D− together over an uninterrupted reference plane, with similar length and few bends. At full speed, a small mismatch is usually less damaging than routing over a plane split or adding large stubs.

Avoid vias if the connector and MCU are on the same side. If a layer change is necessary, change both traces together and provide nearby ground-return vias. Keep the pair away from switching regulator nodes, crystal circuits, and board edges. Fit series resistors only when the MCU or transceiver reference design calls for them, and place them where that design specifies.

For ESP32-C3 and RP2040 examples, compare the USB section against their current reference designs: ESP32-C3 carrier basics and the RP2040 minimal circuit.

Test the failures users will find

Before connecting a computer, current-limit the board and verify there is no VBUS-to-ground short, 5 V reaches the regulator, and no alternate power input back-feeds the unplugged receptacle. Then use a cable matrix:

Cable/source	Orientation 1	Orientation 2
USB-C to USB-C charger	power	power
USB-C to USB-C host	power + enumerate	power + enumerate
USB-A to USB-C host	power + enumerate	power + enumerate

Test cold plug, warm reset, suspend/resume if firmware supports USB, and repeated connector movement. Inspect D+/D− with a USB protocol tool or oscilloscope when enumeration is intermittent. A one-orientation failure points first to CC or duplicate data pins; no C-to-C power but working A-to-C power strongly suggests missing or incorrect Rd resistors. Those are cheap schematic fixes and prominent PCB mistakes that cost a respin, so audit them before release.