Understanding a practical PCB stackup for 2-layer boards

What is actually stacked in a two-layer PCB

From top to bottom, a common finished board contains:

top silkscreen (where used)
top solder mask
top copper
FR-4 dielectric core
bottom copper
bottom solder mask
bottom silkscreen (where used)

Only the two copper layers conduct routed electrical nets. Solder mask is a protective coating with openings over pads; silkscreen is legend ink. Neither is an internal signal layer. The FR-4 core provides mechanical structure and dielectric separation between top and bottom copper.

“1.6 mm, two layer, 1 oz” is a common low-cost configuration, not a definition of two-layer PCB. Fabs offer other finished thicknesses, copper weights, materials, mask colours, and finishes. The selected quote has to match the geometry and mechanical assumptions in the design.

Finished thickness includes more than the core number

The fabricator controls a laminate construction to meet a nominal finished board thickness within its published tolerance. Copper and coatings contribute to the final build, while processing changes material thickness. Do not assume a catalogue “1.6 mm core” plus two exact copper thicknesses is how the fab constructs every 1.6 mm board.

Finished thickness matters for:

• card-edge connectors and slots;
• press-fit or snap-fit enclosures;
• USB receptacle alignment and panel openings;
• stiffness and vibration;
• controlled-impedance calculation;
• through-hole plating aspect ratio.

If a connector accepts only a narrow board-thickness range, place that requirement in the fabrication drawing and select a service whose tolerance supports it. A nominal dropdown value alone may not be enough.

Copper weight is a process input, not a ruler conversion

Copper is often specified in ounces per square foot. One-ounce copper is commonly approximated as 35 µm before processing, but outer layers can receive additional plated copper during fabrication. The finished conductor shape is affected by starting foil, plating, and etching.

Heavier copper can carry more current for a given width and improve thermal spreading, but it normally needs wider minimum features and gaps. Do not copy trace/space rules from a 1 oz capability table into a 2 oz order. The fab trace-and-clearance guide explains how copper weight and layer position qualify published limits.

For current-carrying traces, calculate width from finished copper, allowed temperature rise, length, voltage drop, and cooling. The smallest manufacturable width is not a current rating.

Use one layer as a ground reference where possible

On a simple two-layer board, a productive strategy is:

• place components to keep related circuitry compact;
• route most signals and power on the top;
• preserve as much continuous ground copper as possible on the bottom;
• add ground pour on top where it improves connectivity;
• use stitching vias to join the pours at useful points.

This gives signals a recognizable return structure. Every bottom-layer signal crossing cuts a channel in the ground pour. A bundle that traverses the entire board can split the reference into two regions and force return current around a long path.

Placement has more leverage than late-stage zone filling. Rotate connectors, swap equivalent GPIO assignments when the design permits, and group components so routing does not shred the ground layer. The KiCad ground-plane guide covers zone and stitching details.

Two-layer impedance control is physically constrained

A top-layer trace referenced to bottom copper behaves roughly as a microstrip, but the reference plane is separated by almost the full board thickness. On a typical thick two-layer board, a practical target impedance can require a much wider trace than designers expect. Nearby pours, mask, copper thickness, and the exact laminate properties also affect it.

Do not use a generic online width result without the fab’s actual construction. If controlled impedance matters:

1. Ask whether the fabricator offers impedance control on the selected two-layer service.
2. Obtain its stackup, dielectric thickness, material data, and finished copper assumptions.
3. Use an appropriate field solver or the fab’s calculator.
4. Tell the fab which traces and target impedance require control.
5. Follow its coupon and tolerance process.

For USB, fast clocks, RF, or other edge-rate-sensitive signals, route geometry and continuous return paths still matter even when formal impedance control is not ordered. Keep pairs together, minimize stubs, and do not cross a ground split.

Power distribution needs more than a ground fill

Ground is only half the power path. Route supply rails with widths appropriate to current, keep regulator loops compact, and place decoupling capacitors close to the power pins they serve. A broad top-layer power pour can reduce resistance, but it may also fragment ground or create narrow necks around pads.

Trace the complete current loop: source to load and load back to source. High-current switching returns should not share a thin ground neck with an ADC reference or sensor. Use net highlighting and inspect filled zones with other layers hidden.

Thermal behaviour also depends on copper area, vias, component pad design, airflow, and enclosure. A two-layer copper patch can spread heat, but it is not an infinite heatsink.

Drills connect the two copper layers

Plated through holes and vias have copper barrels that connect top and bottom pads. Their drill, finished-hole size, annular ring, and plating must meet the fab capability. A via only improves electrical connectivity when it lands in same-net copper on both layers.

For ground stitching, place vias beside signal layer transitions, near connectors, and where separated pour regions need a lower-inductance connection. Avoid decorative grids that consume space without a return-path or shielding purpose.

Non-plated holes do not provide an electrical connection. Keep copper away according to the fab’s hole-clearance requirement unless a mounting hole is deliberately plated and grounded.

Know when two layers are the wrong economy

Move to four layers when routing density destroys the ground reference, power distribution becomes a maze, impedance geometry is impractical, emissions or susceptibility risk is high, or the board needs many crossing interfaces. A common four-layer arrangement puts solid ground and power/reference structures much closer to signal layers, producing shorter return paths and easier routing.

Four layers cost more per bare board, but a forced two-layer layout can cost more in area, debugging time, failed compliance, or a respin. Compare the complete product risk, not only the instant-quote price.

Before releasing a two-layer design, use the PCB DFM checklist, confirm the order’s thickness and copper weight, inspect both copper Gerbers, and verify no routed channel has turned the intended ground plane into disconnected decoration.