How to add a ground plane (copper pour) in KiCad PCB Editor

Decide what the plane is supposed to do

A ground pour is copper assigned to the GND net and filled around other board features. On a two-layer board it can provide short return paths, reduce ground impedance, spread heat, simplify routing, and reduce the amount of copper etched away. It is not automatically a continuous “plane” merely because most of a layer looks filled.

Start with a routing strategy. A common two-layer approach is to keep the bottom layer as uninterrupted ground as practical, route most signals on top, and use short bottom-layer crossings only when necessary. Dense routes, wide clearance channels, and badly placed components can cut the pour into narrow necks or disconnected islands.

Do not split ground casually into AGND, DGND, or other names. Different net names force clearance between the copper regions and require an explicit connection. For many mixed-signal boards, one continuous ground with careful placement and return-path control works better than arbitrary splits.

Draw a filled zone on the chosen layer

In PCB Editor, choose the copper layer—often B.Cu for a two-layer board—then select Place → Add Filled Zone. Click near one corner of the board. KiCad opens Zone Properties before you draw the outline.

Set:

• Net: GND (or the deliberate plane net).
• Layer: confirm B.Cu, F.Cu, or the intended inner layer.
• Clearance: the space from different-net copper, governed with other design rules.
• Minimum width: the narrowest copper feature the zone should retain.
• Pad connections: thermal relief or solid, with thermal gap and spoke width.
• Island handling: remove islands that are too small or all disconnected islands, according to the design.

Draw a closed polygon around the usable board area and double-click to finish. The zone outline can follow the board outline; KiCad’s copper-to-edge rule and zone settings determine the filled setback. A simple rectangular or board-shaped polygon is easier to maintain than dozens of tiny contour points.

Press B to refill all zones. An outline without a fill is not manufacturing copper.

Choose thermal relief settings intentionally

Thermal relief connects a pad to the plane with several spokes rather than a solid copper mass. It reduces the heat drawn away during soldering, which helps through-hole and hand-soldered pads reach temperature evenly. Spoke count, spoke width, and thermal gap also determine current capacity and whether DRC sees an acceptably wide connection.

Use solid connection where low impedance or high current truly requires it and the assembly process can heat the joint. Exposed thermal pads, mounting pads, or power connectors may need a footprint-specific decision. Avoid changing the entire ground zone to solid merely to fix one pad; override that pad or footprint when the exception is local.

If a pad looks surrounded by ground but DRC reports it unconnected, inspect whether the thermal spokes actually formed. Clearance, a high minimum width, nearby pads, and zone priority can remove every possible spoke. The unconnected-items guide gives a systematic way to trace that failure.

Keep return paths continuous

Current returns along the path of lowest impedance, which at higher frequencies tends to stay close to the outgoing signal path. A ground pour helps only if copper remains underneath or beside that signal without a slot forcing the return around an obstacle.

After filling, inspect the plane with other layers dimmed. Look for:

• narrow necks between larger ground regions;
• signal bundles that cut the layer from edge to edge;
• traces crossing a gap or split in the reference plane;
• ground pads connected through long, thin tendrils;
• isolated copper islands;
• high-current returns sharing a constricted path with sensitive circuitry.

Move or reroute signals to preserve ground continuity before adding a large number of stitching vias. Vias cannot reconnect two same-layer regions if intervening geometry also blocks useful copper on the other layer.

The two-layer stackup guide explains why a two-layer board cannot provide the same close reference plane as a four-layer stackup and how component placement affects the compromise.

Add stitching vias where they have a job

When both F.Cu and B.Cu contain ground pours, same-net vias join them. Useful locations include:

• beside signal vias, so a return can change reference layers nearby;
• around board edges for RF or emissions control when justified;
• near connectors and decoupling grounds;
• across a narrow ground connection that needs lower inductance;
• around shielded or noisy regions according to the interface design.

Place a via, assign it to GND, and refill. Verify it connects to filled copper on both relevant layers. A via in empty space or inside an isolated island adds a drill without improving the return network.

Spacing should follow the signal frequencies and enclosure requirements, not an aesthetic grid copied from another board. Dense via fences consume routing room and fabrication drill time.

Manage overlapping zones and priorities

Boards often contain a large ground zone plus smaller power or high-current zones. When two different-net zones overlap, priority decides which is allowed to occupy the area; clearances then separate the fills. KiCad 9’s Zone Manager provides a consolidated view of zone properties and priorities.

Give a higher priority only to a zone that deliberately needs to win. Refill after every priority or outline change and inspect the result. A power island can unintentionally slice the ground reference beneath signals even when both zones individually look sensible.

Rule areas and keepouts can prohibit zone fill under antennas, around mounting hardware, or in high-voltage regions. Make those shapes visible during review and document why they exist.

Run DRC on the filled result

After refilling, run Inspect → Design Rules Checker. Ground-zone problems can appear as unconnected items, isolated copper, clearance violations, copper slivers, or connections narrower than the configured minimum. The KiCad DRC violations reference explains what each class is measuring.

Then inspect the Gerber copper layers. Confirm that the plot contains the same fill seen in PCB Editor, thermal spokes are present, and no island or cutout appeared unexpectedly. Save the board after the final refill so command-line DRC and fabrication exports use current zone data.

A good ground pour is not the maximum possible area of green or red on screen. It is a deliberate, connected return structure whose necks, clearances, thermal connections, and relationship to signal paths have all been reviewed.