KiCad DRC violations explained: what each one really means

Read the resolved rule before moving copper

KiCad’s Design Rules Checker compares the board against constraints from File → Board Setup, net classes, custom .kicad_dru rules, footprint geometry, and the schematic. A DRC marker is not just a complaint about two coordinates; it is the result of a particular rule being resolved for particular objects.

Open Inspect → Design Rules Checker, run DRC with zones refilled, then select a violation. KiCad highlights the involved objects and, for clearance and constraint failures, can show the resolved requirement and actual value. Right-clicking a clearance marker and opening the clearance resolution information is far more useful than guessing which global setting produced it.

Fix the source of the mismatch. Moving a trace by 0.05 mm may silence one marker while preserving a bad net class, an incorrect footprint, or a manufacturing rule that will fail elsewhere.

Copper spacing and accidental shorts

These messages describe relationships between conductive objects:

Violation	What it means	First place to look
Clearance violation	Copper on different nets is closer than the resolved electrical or physical clearance.	Net classes, custom rules, then local routing.
Shorting items	Two conductive objects assigned to different nets overlap or touch.	Track endpoints, vias, pads, and freshly filled zones.
Hole clearance violation	A drilled hole is too close to copper on a common layer.	Via placement, mounting-hole footprint, copper-to-hole constraint.
Board edge clearance violation	Copper is closer to Edge.Cuts than allowed. Routed slots also count as edges.	Board outline, castellations, edge connectors, copper-to-edge rule.
Creepage violation	The surface path between nets is shorter than a configured creepage constraint.	High-voltage custom rules and slots intended to extend creepage.

A clearance violation is edge-to-edge, not centerline-to-centerline. Its required distance may come from the board minimum, either object’s net class, or a custom rule. If the actual gap is 0.14 mm and the rule says 0.20 mm, decide whether 0.20 mm expresses the fab and electrical requirement before rerouting.

A shorting items marker is normally a real electrical error. Exceptions such as net ties should be modeled with an intentional net-tie footprint, not waived wherever two named nets happen to meet. Refill zones with B before judging a zone-related short because stale fills do not represent the output you will plot.

Width, annular ring, and connection geometry

Track width means a segment is outside the allowed minimum or maximum. The width selected in a net class is the router’s preferred width; it is not automatically a DRC minimum. The board-level minimum track width or a custom width constraint supplies the enforceable limit. Set those values from the chosen process, using a conservative starting point described in minimum trace width and clearance.

Annular width means the copper ring around a drilled pad or via is too small. The ring is half the difference between pad diameter and finished hole diameter for a circular feature. Increasing only the pad diameter may solve it, but first confirm the footprint and drill size against the component drawing. A lead that needs a 1.0 mm finished hole should not be forced into 0.8 mm merely to gain ring width.

Copper connection too narrow detects a neck in connected copper below the minimum connection width. It often appears where a zone squeezes between pads or where thermal spokes are too thin. Changing a track elsewhere will not fix that geometry; adjust zone clearance, thermal settings, pad layout, or the constraint.

Via is not connected or is connected on only one layer means the via is not doing a via’s normal job of joining copper across layers. It may be an abandoned via left after rerouting, a stitching via whose zone is stale, or a net mismatch. Refill zones, inspect both layers, and delete it if it serves no purpose.

Unrouted and dangling connections

Unconnected items means KiCad’s connectivity engine still sees pads on the same net without a continuous copper path. The ratsnest line may be hidden under a zone, between overlapping pads, or only a few micrometres long. It is not a cosmetic warning: the manufactured net can be open. The focused guide to fixing unconnected items covers zone fill, pad numbers, track endpoints, and misleading visual overlaps.

Track has unconnected end is narrower. One end of a track segment does not terminate on another track, via, pad, zone, or copper shape. It may be an intentional antenna element or test feature, but more often it is a leftover stub or a segment that stops just short of a pad. Zoom in, inspect the endpoint properties, and remove or reconnect it.

Do not waive either message solely because the 3D view looks right. The 3D renderer shows shapes, not electrical continuity.

Footprints, courtyards, and board outline

Courtyards overlap means two footprint courtyard shapes intersect, or violate a custom courtyard clearance. Courtyards represent the assembly and rework envelope, not copper spacing. Check actual package bodies, pick-and-place tolerances, connector mating access, and hand-soldering needs before accepting an overlap.

Footprint has malformed courtyard means the graphics on F.Courtyard or B.Courtyard do not form closed outlines. Edit the project footprint and close the geometry. Footprint has no courtyard is ignored by default in many configurations, but it is worth fixing when an assembler will use the data.

Board has malformed outline means Edge.Cuts does not form valid, closed, non-self-intersecting contours. Duplicate lines, microscopic gaps, overlapping arcs, and stray marks can all trigger it. This is a release blocker because the fabricator derives routing from that layer.

Items not allowed means an object occupies a rule area that disallows its type, or a custom rule uses a disallow constraint. Inspect the rule area properties rather than dragging the item until the marker disappears.

Zone and solder mask findings

Isolated copper fill is a filled zone island with no same-net connection. A floating copper island has no guaranteed potential and can create etching or coupling problems. Prefer removing islands in zone properties, or change the layout so the copper has a deliberate connection.

Copper sliver marks a narrow wedge-shaped remnant that may not manufacture reliably. It is often caused by acute zone geometry between pads or traces. Adjust the route, zone outline, clearance, or minimum copper width; do not assume a fab will preserve a feature that your own rules identify as fragile.

Solder mask aperture bridges items with different nets means one mask opening exposes copper belonging to multiple nets. During assembly, that shared opening removes the insulating mask web between pads and increases bridge risk. The remedy depends on pitch and fab capability; the solder mask bridge guide explains when mask dams can exist and when the footprint should intentionally merge openings.

Schematic parity violations

When parity checking is enabled, DRC can report missing footprint, extra footprint, duplicate footprints, net conflicts, and mismatched fields. These say the PCB is not a faithful physical instance of the schematic. Run Tools → Update PCB from Schematic and review the proposed changes instead of manually renaming pads or references.

An extra board-only mounting hole can be legitimate if it is a footprint with no schematic counterpart; model or exclude it consistently. A missing IC footprint is not legitimate merely because the rest of DRC is green.

Exclusions are reviewed engineering decisions

KiCad lets you exclude individual markers and change default severities. Use that mechanism for specific, understood cases such as a deliberately open antenna trace. Attach a concise reason so another reviewer can distinguish intent from cleanup avoidance.

Before release, run DRC again after refilling zones, include all relevant severities, inspect the exclusions list, and save a report. A clean marker list is only meaningful when the rules match the intended manufacturer and the exceptions remain explainable.