Reset and Boot Circuits for ESP32 and RP2040

Reset and boot are separate decisions

Reset forces a processor into a known startup sequence. Boot straps tell its ROM what to do during that sequence. The control may share a button or programmer, but the signals are not interchangeable.

The reliable design pattern is:

defined normal level -> explicit override -> reset samples override -> release

Every control needs a known unpressed state, a way to invoke recovery without working application firmware, and test access after the board is assembled. ESP32-C3 and RP2040 implement this pattern differently, so never copy one chip’s BOOT circuit to the other.

This distinction is an important check when you vibecode an ESP32 board, because an otherwise plausible generated reset circuit may belong to another MCU family.

ESP32-C3: EN resets, GPIO9 selects download mode

On ESP32-C3, CHIP_EN (often labeled EN) enables the chip high and holds it in reset low. It must not float. Espressif’s chip guidance recommends an RC delay—commonly 10 kΩ from EN to 3.3 V and 1 µF from EN to ground—then a normally open RESET button from EN to ground. Use the selected module’s reference design for final values.

The RC lets the 3.3 V rail stabilize before EN rises. It is not a complete brownout supervisor. A battery charger, slowly ramping rail, or frequently switched supply may need a reset supervisor with a defined threshold and hysteresis.

ESP32-C3 samples GPIO2, GPIO8, and GPIO9 as strapping pins. For ordinary SPI boot, GPIO9 must be high. A manual BOOT circuit uses a pull-up on GPIO9 and a normally open button to ground. The download sequence is:

1. Hold BOOT, pulling GPIO9 low.
2. Press and release RESET, so EN returns high while GPIO9 is low.
3. Keep BOOT held through strap sampling, then release it.
4. Download over UART or integrated USB Serial/JTAG as configured.

Do not add a large capacitor to GPIO9; it can hold the strap low after the button is released. Check anything else on GPIO2, GPIO8, or GPIO9. A peripheral output, LED, or strong external pull can change the sampled state. Espressif recommends pulling GPIO2 high because of possible glitches even though GPIO2 does not distinguish the normal and joint-download modes in the basic boot table.

The ESP32-C3 carrier guide covers power and antenna constraints around this circuit.

ESP32 automatic download needs the proven logic

A USB-UART bridge can use DTR and RTS to drive GPIO9 and EN, allowing tools such as esptool to reset the target into the ROM downloader. Do not connect the handshake outputs directly without checking polarity and simultaneous states. Terminal programs often assert both lines together; a naive circuit can then hold the chip permanently in reset.

Copy the transistor network from the current Espressif development-board reference that matches the target and bridge logic levels. Preserve its pull resistors and capacitor, then simulate or truth-table these cases:

DTR/RTS state	EN	GPIO9	Expected result
Idle	high	high	Run application
Download sequence	pulse low then high	low during sample	ROM downloader
Both asserted	not stuck low	defined	No permanent reset

Keep manual buttons and accessible pads even when automatic download is fitted. They separate a tool/driver problem from a target hardware problem.

RP2040: RUN resets, QSPI_SS participates in BOOTSEL

RP2040’s RUN pin is an active-low global reset. A manual RESET button pulls RUN to ground; the released level and optional capacitance should follow Raspberry Pi’s current minimal reference. Expose RUN on a test pad so a debugger or fixture can reset the target.

RP2040 does not have a pin named BOOTSEL. Its ROM samples QSPI_SS, which is also the external flash chip-select signal. The reference topology is:

RP2040 QSPI_SS ------ flash CS
        |
        +--- 1 kΩ --- BOOTSEL button --- GND
        |
        +--- optional 10 kΩ pull-up footprint --- 3V3

The 1 kΩ matters. During normal execution, RP2040 actively drives QSPI_SS to access flash; the resistor limits the effect of a held button. A direct short to ground can prevent flash access. The optional pull-up requirement depends on the selected flash and reference-design guidance.

To enter ROM USB boot, hold BOOTSEL and then reset by pulsing RUN low or applying power. Release reset first; release BOOTSEL after the ROM has sampled it. The device should enumerate as its mass-storage bootloader. The flash connection and full power circuit are detailed in the RP2040 minimal design.

Keep recovery independent from USB

USB is convenient but can be the failed subsystem. Add SWD pads on RP2040 (SWDIO, SWCLK, ground, voltage reference, optionally RUN). On ESP32-C3, expose UART0 TX/RX, ground, 3.3 V reference, EN, and GPIO9. Mark signal direction from the target’s perspective and use a keyed fixture or asymmetric pad pattern.

Do not let an external programmer power the target accidentally through I/O. Decide whether its voltage-reference pin is an input sense or a power feed, and label it. If the target may be self-powered, use a bridge or probe that tolerates that arrangement.

Test power-up states, not just the buttons

Run at least these cases on assembled hardware:

• ten cold starts at minimum and maximum intended input voltage;
• reset while application firmware is busy;
• manual recovery with application flash blank and corrupted;
• programmer attached and detached;
• each external peripheral attached and unpowered;
• slow power ramp if the product uses a battery or load switch;
• automatic download followed by a normal reboot.

Observe EN/RUN, the boot strap, and the main rail together on an oscilloscope when a failure is intermittent. Confirm the strap has reached a valid level before the sampling window and that reset is held for its minimum duration.

Common failures are a four-pin tactile switch rotated 90 degrees, a reset capacitor placed on the boot strap, missing pull resistors, a peripheral fighting a strap, and an RP2040 button shorting flash CS. These all look simple on a schematic and can produce a full PCB respin, which is why the recovery sequence belongs in the board’s release test plan.