PCB Layout Review Checklist: 30 Checks Before You Plot

What this checklist covers

A DFM check asks whether the fab can build the board (DFM checklist). A layout review asks whether the board will work and be usable once built. The two overlap but catch different problems, and a design-rule check passes happily on a board with a reversed polarity mark. Run this list after DRC is clean and before plotting. Tick each item or write down why it does not apply.

Power and ground

1. Every IC power pin has a decoupling capacitor placed beside it, with the capacitor between the pin and ground and the short path through the pad, not a long trace (where to place them).
2. Supply traces are wide enough for the current, using a calculation for the copper weight and allowed temperature rise, not the fab minimum.
3. Ground is continuous under fast signals; there are no unintended splits in a ground pour.
4. Regulator input and output capacitors match the regulator datasheet, including the type and value it requires for stability.
5. Bulk capacitance exists near the power input and near large loads.
6. Test points or headers exist for main rails.

Connectors and interfaces

7. Pin 1 and orientation of every connector match the mating part and the schematic.
8. USB data lines are routed as a pair, kept short, and not split by vias where avoidable; USB-C has the CC resistors and ESD protection a sink or source needs (USB-C power, CC, and ESD).
9. Connectors that take force sit at the board edge and have mechanical support (through-hole pins or mounting holes).
10. Programming and debug headers are accessible after assembly.
11. Hot-plug connectors have protection appropriate to the interface.

Clocks, resets, and strap pins

12. The crystal is close to the chip, with load capacitors matched to the crystal’s specified load, and no unrelated traces routed underneath it.
13. Reset and boot pins have the pull-ups, pull-downs, and capacitors the MCU datasheet asks for (reset and boot circuits).
14. Strapping pins are not accidentally loaded by LEDs or connectors that change their level at power-up.

Analog and RF

15. Analog inputs are kept away from switching nodes, clocks, and inductors.
16. Any module with an onboard antenna has its keepout respected on every layer (rule areas).
17. Antenna traces and matched networks follow the vendor reference layout, including the ground clearance they specify.

Components and footprints

18. Each footprint was checked against the datasheet’s land pattern, not just the library name (footprint vs symbol).
19. Polarised parts (diodes, electrolytic and tantalum capacitors, LEDs) have a visible marking that matches the footprint.
20. Component values and part numbers in the BOM match the schematic (BOM with real part numbers).
21. Parts have stock and a second source where the project needs one (availability check).
22. Heavy or tall parts do not collide with the enclosure or with each other.

Silkscreen, marking, and assembly

23. Silkscreen text is readable, not over pads, and reference designators are present where hand assembly needs them.
24. The board has a name, revision, and date on a copper or silk layer.
25. Mounting holes and fiducials are present if the assembly process needs them.
26. Pick-and-place data and BOM columns line up with each other (pick-and-place files).

Final consistency

27. ERC and DRC pass, and every exclusion has a written reason (DRC settings).
28. Schematic and board are in sync with no unexpected parity differences.
29. The exported Gerbers and drill file were opened in a viewer and look right (Gerber viewer check).
30. Someone other than the author has looked at the board, even for ten minutes. Fresh eyes find polarity, orientation, and label errors faster than a tool.

Using the checklist well

Do not treat it as a pass-fail form. Its value is in the items that make you stop. If a board is simple, half of these will not apply; mark them as not applicable rather than skipping them silently. When you find an error, add a new line to your own copy of the list. Over a few projects it becomes a record of the mistakes you tend to make, and that record is more valuable than any generic list.

Items 27 to 29 can be automated. The MakeIRL preflight gate runs the electrical rules check, the design rules check, parity, BOM completeness, and export integrity and reports which ones block the order. It is a deterministic check, not a design review; items 1 to 26 still need a person.