Castellated PCB Manufacturing: Half-Hole DFM and Assembly

This is a board attribute manufacturing profile for castellated PCB. The board profile below is a process-specific baseline that still needs order-specific confirmation, not a guaranteed price or capability.

Capabilities, prices, lead times, approved materials, assembly stock, shipping, and taxes change. Requote the exact revision and retain the supplier's order-specific confirmation before release.

• Define module outline, hole diameter, pitch, annulus, edge breakout, board thickness, parent-board land overlap, fillet visibility, antenna keepouts, and mating cycles.
• Choose the attribute because a measured electrical, thermal, mechanical, assembly, or lifecycle requirement needs it; document the requirement and the simpler alternative considered.

Mark castellations explicitly, use the supplier's minimum pitch and hole rules, and panelize without V-scores or tabs crossing the plated half holes.

• Obtain the actual stackup, material, tolerance, coupon, panel, and process notes before routing; the same marketing label can describe materially different constructions.

• Provide placement fiducials and paste tuned to parent lands; side fillets must remain visible and module bow controlled.
• Check how the fabrication choice changes stencil, reflow, handling, depanelization, warpage, inspection, repair, and component compatibility.

Validation plan:

• Inspect edge plating, burrs, coplanarity, every side fillet, and continuity; mechanically load representative modules and exercise every interface.
• Measure the property that justified the attribute—impedance, temperature rise, bend life, solderability, flatness, or interconnect reliability—on representative built boards.

Cost drivers:

• Special routing/plating, panel rails, lower edge yield, module handling, inspection, and parent-board assembly drive cost.
• Special materials and process steps can add tooling, minimum quantity, engineering review, lower panel yield, and longer queues even when raw board area is unchanged.

• Ordinary plated holes placed on Edge.Cuts do not automatically become clean, accepted castellations at every fabricator.
• Paying for an attribute without encoding its constraints in the design produces a more expensive board with no guaranteed performance benefit.

Ask the fabricator directly:

• What minimum pitch, hole, annulus, edge breakout, and board thickness are qualified for castellations?
• How will panels support the routed edge without tabs or burrs damaging half holes?

1. S1Schematic/PCB parity and unresolved connectivity. Run ERC, DRC with schematic parity, and netlist comparison for the castellated PCB release; explain every exclusion rather than suppressing it globally.
2. S2Quoted fabrication-profile compliance. Compare saved copper, holes, mask, outline, and plated holes bisected by a controlled routed edge constraints with the exact quoted stackup and option set.
3. S1BOM, placement, polarity, and output identity. Require exact MPNs, matched BOM/CPL reference sets, reviewed rotations, one clean outline, and fabrication outputs regenerated from the approved castellated PCB source revision.