Generate a Radio Module Carrier with AI: Refusal Design Guide

MakeIRL's generator treats a radio module carrier prompt as a module carrier. Current status: refused.

Current policy refuses RF requests even when the radio is inside a module. The checked ESP32-C3 carrier seed must not be marketed as physically verified RF carrier output.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact module MPN/revision, certifications and conditions, integrated/external antenna, reference layout, bands/regions, and required range
2. Host interfaces/pins, boot/reset, peak/sleep current, supply ripple, programming, firmware/update, and regulatory identifiers
3. Board edge and antenna keepout, enclosure/battery/cable/hand proximity, mounting, ground strategy, shielding, and RF test plan

Block plan:

• No new RF module carrier is composed under current policy
• Future block requires immutable module footprint/pin map, antenna keepout, power, reset/boot, and physical evidence
• Power/host blocks remain subordinate to RF certification and enclosure review

Interfaces: future UART/I²C/slow SPI host, boot/reset/programming, RF remains inside an approved module. Power plan: Future carrier must cover transmit peaks with 30% headroom and clean decoupling; no generated RF power, matching, battery, or SMPS.

• A future block must place the module at the correct edge, enforce all antenna copper/component/board keepouts, and control return and supply loops.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Today the correct result is refusal. Future checks include exact module revision, pin/footprint parity, keepout geometry, power peaks, boot circuit, and certification conditions.
2. S1Catalog and exact-MPN provenance. Every radio module carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review module certification scope, antenna/enclosure detuning, regional bands, EMC/coexistence, firmware, security, labeling, and physical RF measurements.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Pre-certified does not mean the final host product is automatically compliant, and violating the antenna reference layout can destroy range.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Future hardware needs rail/current tests plus conducted/radiated output, harmonics, receiver sensitivity or range, enclosure detuning, coexistence, ESD, and compliance review.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse all radio carriers, custom antenna/matching, RF certification claims, and unknown modules under current policy.
• The existence of a checked ESP32-C3 electrical block does not override explicit RF refusal or physical verification status.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.