Generate an ESP32-C3 Carrier with AI: Current V2 Design Guide

MakeIRL's generator treats a ESP32-C3 carrier prompt as a module carrier. Current status: current checked demo.

This is the only current demonstrated composition: ESP32-C3-WROOM-02 carrier + USB-C power + Qwiic/status LED. Blocks are checked, not physically verified, and current PCB output still requires gate resolution and review.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact ESP32-C3-WROOM-02 variant/revision, required GPIOs, boot/programming method, UART, reset behavior, and module antenna
2. USB power/current, Qwiic usage and address plan, status LED behavior, connector, external loads, and total BOM/board limits
3. Board outline/mounting, antenna edge/keepout, USB/Qwiic faces, height zones, enclosure, test access, and human reviewer

Block plan:

• Current checked esp32-c3-carrier block with EN reset RC and 3.3 V decoupling
• Current checked usb-c-power block with two CC pulldowns, ESD, bulk capacitance, and AP2112K
• Current checked qwiic-status-led block with 4.7 kΩ pull-ups and GPIO LED

Interfaces: I²C/Qwiic, GPIO/status, UART programming/debug. Power plan: 5 V power-only USB-C into the checked AP2112K 3.3 V block, with compatibility budgeting and 30% current headroom.

• Place the module antenna at the board edge with its keepout, anchor USB-C, keep reset/bypass local, and separate Qwiic/LED routing from the antenna zone.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check EN RC and decoupling, USB CC/ESD and connector redundant pins, Qwiic pull-ups/voltage, module pin/footprint, antenna keepout, programming access, and every unrouted/DRC finding.
2. S1Catalog and exact-MPN provenance. Every ESP32-C3 carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review checked-not-verified evidence, RF/enclosure behavior, boot straps, regulator thermal/current, USB mechanics, GPIO assignment, pull-ups, source files, and all gate findings.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• The current deterministic route has documented review/block findings around residual USB-C connections; generated artifacts cannot be described as ready to order without resolution.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• After an engineer resolves the gate, inspect Gerbers/BOM/CPL, current-limit bring-up, verify 3.3 V/EN/programming, USB orientation, Qwiic, LED, radio/enclosure performance, and thermal load.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse custom RF/antenna changes, batteries, motors, SMPS, high-speed, unknown modules, or loads outside 12 V/2 A and 40 lines.
• Never call the current blocks physically verified or imply the generated candidate is autonomously fab-ready.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.