Vibecode a Status Light PCB with AI: Current and Gate Checks

MakeIRL's generator treats a status light prompt as a self-contained project board. Current status: current checked demo.

The checked Qwiic/status-LED block can provide one low-current indicator as part of the ESP32-C3 demo. More channels, high brightness, RGB, or external loads need new verified blocks.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. LED MPN/color/Vf, target current/brightness, viewing angle, polarity, ambient light, duty, and resistor tolerance
2. Controller GPIO, active-high/low behavior, boot/reset state, PWM need, supply, and current limits
3. Lens/light-pipe or panel geometry, board side, orientation mark, connector, enclosure, and inspection method

Block plan:

• Current checked ESP32-C3 carrier
• Current checked Qwiic/status-LED block with fixed resistor/topology
• Current checked USB-C power block

Interfaces: GPIO indicator, optional PWM within GPIO limits, I²C/Qwiic expansion. Power plan: Low-current LED from the cataloged 3.3 V rail; total current remains far below the envelope.

• Place the LED against the lens or viewing aperture, keep polarity visible, prevent light leakage where relevant, and keep the GPIO route away from boot conflicts.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify LED anode/cathode, resistor value and power, GPIO current and boot state, exact block topology, supply, and status meaning.
2. S1Catalog and exact-MPN provenance. Every status light block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review perceived brightness and color, active polarity, startup flash, light pipe alignment, accessibility, GPIO drive, and current budget.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A resistor selected from typical Vf can overdrive another color/bin, and a boot-time GPIO state can flash a misleading alarm.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Measure LED current across supply and temperature, observe startup/reset/PWM states, inspect color/brightness and lens alignment, and verify status semantics.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse high-power lighting, strips, matrices, constant-current conversion, or unknown LED loads.
• Current support is one checked low-current status topology, not a general lighting generator.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.