Vibecode a Smart Button PCB with AI: Low-Power Gate Guide

MakeIRL's generator treats a smart button prompt as a self-contained project board. Current status: in envelope needs block.

A USB-powered wired button is inside the intended low-speed envelope after a verified switch block exists. BLE or battery operation is refused by the current RF/lithium policy.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Switch MPN, actuator force/travel, normally-open/closed behavior, pull state, debounce and wake requirement
2. Wired or wireless role, exact module, power source, sleep target, status behavior, and programming
3. Button location, cap/enclosure stack, ESD exposure, mounting, connector, and service access

Block plan:

• Current checked ESP32-C3 carrier for a wired/networked demo
• Verified human-input switch/debounce block
• Current checked USB-C power and status/Qwiic blocks when their exact functions fit

Interfaces: GPIO input/wake, status GPIO, optional I²C expansion. Power plan: Current path uses USB power; battery and charging are not generated. Sleep leakage and LED duty still require a budget.

• Reference the switch to the enclosure datum, keep its ESD path short, separate mechanical load from solder joints, and leave boot/programming access.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check pull direction and value, button-to-GPIO net, boot-strap conflicts, debounce components, LED resistor, connector ESD, and current budget.
2. S1Catalog and exact-MPN provenance. Every smart button block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review boot behavior when held, contact bounce, wake-current path, accessibility, switch cycle rating, cap mechanics, ESD, and whether radio is module-contained.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A button on a boot-strap pin can trap the module in the wrong mode, and a status LED can dominate the sleep-current budget.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Cycle the switch mechanically, log bounce, test press during reset and power-up, measure sleep/wake current, perform ESD testing, and verify enclosure feel.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse lithium charging, coin-cell claims, BLE antenna design, or an unknown wireless module.
• A wireless smart button remains out of current scope even when its digital switch circuit is simple.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.