makeIRLPCB engineering field guide

Manufacturing & fabrication intents

PCB Manufacturing for Wearable Electronics: Practical Guide

Plan wearable PCB fabrication around thin rigid boards, skin-side height, battery safety, flex strain, ready for fabrication-specific DFM review.

Practical PCB integration · KiCad 9 · Manufacturing gate

Manufacturing plan for wearable electronics

This is a use case manufacturing profile for wearable electronics. The board profile below is a starting point to confirm against an exact fabricator quote, not a guaranteed price or capability.

Intentwearable electronics
Layers2 layers for simple low-speed wearables; 4 layers when radio return paths or density justify them
Copper1 oz outer copper is a common rigid starting point
Thickness0.8–1.0 mm rigid FR-4; thinner only after enclosure and assembly review
FinishENIG for fine pitch and flat pads; lead-free HASL can suit coarser designs
Special processSmall-component assembly, rounded outline, and optional rigid/flex construction

Capabilities, prices, lead times, approved materials, assembly stock, shipping, and taxes change. Requote the exact revision and retain the supplier's order-specific confirmation before release.

Design priorities and fabrication notes

  • Prioritize total thickness, skin-side smoothness, antenna and battery placement, rounded edges, charging access, strain relief, and a power budget that includes radio peaks.
  • Freeze connectors, board outline, mounting, height zones, power budget, and environmental assumptions before treating the stackup as final.

Keep copper and vias away from repeated-bend or snap-fit zones, check minimum routed corner radius, and document coating exclusions at electrodes or sensors.

  • Apply one named fabricator capability profile to traces, clearances, drills, annular rings, edge setback, mask dams, and panel rules; nominal defaults are not a quote.

Assembly, validation, and cost drivers

  • 0402 parts and low-profile connectors raise placement and rework demands; agree component height, bottom-side population, cleaning, and battery attachment before quoting.
  • Give every fitted reference an exact MPN and footprint, keep BOM and placement reference sets identical, and inspect the assembler's rotation preview before release.

Validation plan:

  • Fit the real enclosure and strap, bend and drop representative assemblies, measure radio and battery behavior on-body, and test sweat or condensation protection appropriate to use.
  • Bring up first articles on a current-limited supply, record rail and interface measurements, and test the physical loads, cables, enclosure, and environment the board was designed for.

Cost drivers:

  • Thin cores, four layers, flex tails, fine-pitch assembly, coating, batteries, and low-volume mechanical fixtures dominate more than the small board area.
  • Area, layer count, panel utilization, drill count, finish, controlled processes, component variety, setup, and test time usually matter more than a headline per-board price.

Failure modes and questions for the fabricator

  • A rigid board can crack solder joints when the enclosure flexes, while an antenna that worked on the bench can detune next to the body and battery.
  • A clean fabrication check proves encoded geometry, not circuit function, thermal margin, EMC, regulatory compliance, or mechanical fit.

Ask the fabricator directly:

  • What minimum thickness and panel support can carry the chosen 0402 and connector mix without excessive bow?
  • How will coating, cleaning, battery attachment, and flex or strap strain relief be handled and inspected?

Gate checks for wearable electronics

  1. S1Schematic/PCB parity and unresolved connectivity. Run ERC, DRC with schematic parity, and netlist comparison for the wearable electronics release; explain every exclusion rather than suppressing it globally.
  2. S2Quoted fabrication-profile compliance. Compare saved copper, holes, mask, outline, and small-component assembly, rounded outline, and optional rigid/flex construction constraints with the exact quoted stackup and option set.
  3. S1BOM, placement, polarity, and output identity. Require exact MPNs, matched BOM/CPL reference sets, reviewed rotations, one clean outline, and fabrication outputs regenerated from the approved wearable electronics source revision.

Check the design before fabrication

Run the release gate on the KiCad project intended for wearable electronics.

Check a KiCad project