Generate a Seeed XIAO Carrier with AI: Scope and Gate Checks

MakeIRL's generator treats a Seeed XIAO carrier prompt as a module carrier. Current status: in envelope needs block.

XIAO carriers are named in the intended envelope, but no XIAO variant is in the current catalog. Pin maps and radio/battery behavior differ, so the exact variant needs a verified block.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact XIAO variant/revision, pin map and bottom pads, USB ownership, radio/antenna if any, boot/reset, programming, and 3.3/5 V behavior
2. Peripheral pins, connector modules, aggregate current, battery/charging pins and explicit non-use, protection, and backfeed rules
3. Module orientation and overhang, antenna/USB keepout, socket versus solder, mounting, enclosure height, test, and replacement access

Block plan:

• Future verified exact-variant XIAO module/footprint block
• Verified Qwiic/status and low-speed connector blocks
• No battery/charging or RF use unless separately allowed and physically verified

Interfaces: GPIO/I²C/UART/slow SPI, module-owned USB, variant-specific power pins. Power plan: Use only documented module power input/output within the envelope; prohibit accidental dual-source backfeed and battery/charge paths.

• Lock module outline/overhang, keep access to module USB/reset, preserve antenna keepout for radio variants even if radio use is refused, and align castellated rows.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify exact variant pin map, footprint/row pitch, module orientation, power direction/backfeed, USB clearance, battery pins unused, and peripheral compatibility.
2. S1Catalog and exact-MPN provenance. Every Seeed XIAO carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review variant differences, module regulators and current, USB access, radio certification/keepout, battery pins, boot behavior, stacking height, and replacement.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Two XIAO boards share an outline but can differ in MCU, pin functions, radio/antenna, power behavior, and bottom-pad details.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• A future block needs mechanical fit across real headers/sockets, power/backfeed, boot/programming, module USB, every exposed pin, Qwiic, current, and thermal tests.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse an unspecified XIAO, battery charging, radio use, or invented bottom-pad functions.
• Mechanical outline compatibility does not establish electrical compatibility across XIAO variants.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.