Vibecode an LED Controller PCB with AI: Power and Gates

MakeIRL's generator treats a LED controller prompt as a self-contained project board. Current status: needs clarification.

A few low-current indicator channels could fit the envelope after a verified driver block exists. Strip or high-power control may exceed 2 A or require unsupported switching/power blocks and must be refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. LED load type, supply, per-channel and simultaneous current, PWM rate, cable, and fault current
2. Exact cataloged driver/MOSFET, gate network, flyback need, fuse, reverse-polarity and ESD strategy
3. Connector MPN, thermal ambient, enclosure, mounting, test points, and safe default state

Block plan:

• Cataloged controller/module carrier
• Verified low-side LED driver block with current and thermal evidence
• Verified protected 12 V input and keyed output connector blocks; no invented high-power topology

Interfaces: GPIO/PWM, low-voltage load outputs, optional I²C control only through a supported block. Power plan: At most 12 V SELV and 2 A total, with calculated connector, trace, via, fuse, and device margins; no generated SMPS.

• Keep load and PWM returns out of logic reference paths, use broad current copper, place protection at connectors, and spread driver heat without heating the MCU.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check channel net mapping, default gate states, flyback/protection polarity, current-path necks, thermal-pad connection, total budget, and clearance to logic.
2. S1Catalog and exact-MPN provenance. Every LED controller block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review semiconductor safe operating area, PWM switching loss, connector ratings, fuse coordination, LED load behavior, enclosure heat, and fault containment.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A channel that passes at low duty can overheat at simultaneous full duty, and an open gate pulldown can flash LEDs during reset.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Load all channels together, record current and temperature, inspect PWM edges and default state, and test open, short, reverse, and hot-plug conditions safely.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse totals above 2 A, mains lighting, switch-mode constant-current design, unknown strips, or uncataloged power semiconductors.
• Ask for load current and thermal data; 'drive some LEDs' is not enough to choose copper, connector, or driver.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.