Vibecode an LED Matrix PCB with AI: Current and Gate Guide

MakeIRL's generator treats a LED matrix controller prompt as a self-contained project board. Current status: needs clarification.

A small low-current matrix may fit after a verified matrix-driver block exists. Large panels, high peak current, or switch-mode LED power are outside the current generator.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Matrix dimensions, LED Vf/bin, row/column polarity, scan ratio, peak/average current, refresh and brightness
2. Exact driver and current-setting components, controller timing, blanking behavior, and power-on state
3. Panel pitch, optical orientation, connector, supply, heat path, enclosure, and camera/flicker requirement

Block plan:

• Cataloged MCU/module carrier
• Verified row/column or constant-current matrix-driver block
• Verified 5 V input, protection, bulk capacitance, and connector blocks within the current envelope

Interfaces: SPI or GPIO scan, row and column drive, programming/debug. Power plan: 5 V SELV with peak, average, inrush, and decoupling budgets stated; stay below 2 A and avoid generated converters.

• Keep matrix geometry exact, balance high-current row/column copper, place bulk and local bypassing near drivers, and separate scan returns from controller ground sense.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Prove every LED polarity and coordinate, current-set value, row/column driver rating, blanking default, instantaneous current path, and total power budget.
2. S1Catalog and exact-MPN provenance. Every LED matrix controller block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review multiplex peak-current limits, duty derating, visual flicker, ghosting, thermal rise, LED binning, optical orientation, and firmware timing.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Average current can look safe while scan peaks exceed LED or driver pulse limits, and overlap between rows can create ghost pixels and excess current.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Display all-on, checkerboard, single-row, and walking-pixel patterns; measure peak current, refresh, ghosting, brightness uniformity, flicker, and temperature.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse matrices whose peak current exceeds 2 A or whose power requires an uncataloged converter or high-energy driver.
• Refuse an unspecified LED panel or pinout; matrix coordinate truth must come from a reviewed drawing.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.