Vibecode a Power Monitor PCB with AI: Accuracy and Gates

MakeIRL's generator treats a power monitor prompt as a self-contained project board. Current status: in envelope needs block.

A low-voltage ≤12 V/2 A monitor can fit after verified voltage/current measurement blocks exist. It cannot generate a converter, charger, mains meter, or revenue-grade instrument.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Voltage/current range and transients, direction, bandwidth, update and energy integration interval, burden, and fault energy
2. Monitor/shunt/divider MPNs, accuracy/temperature budget, calibration, alert behavior, and counter retention
3. Source/load connectors, grounding, USB/data interface, enclosure heat, isolation assumptions, and test access

Block plan:

• Cataloged controller/module carrier
• Verified voltage plus Kelvin current-monitor block
• Protected source/load connectors, fuse strategy, and low-voltage reporting block

Interfaces: I²C measurement, UART/I²C reporting, DC force path. Power plan: Pass at most 12 V/2 A, account for shunt and copper loss, and power logic without creating an unreviewed backfeed path.

• Keep force and sense networks separate, place voltage protection at entry, avoid shared connector drops, and thermally isolate precision resistors from hot copper.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check voltage divider and ADC range, shunt Kelvin topology, monitor common-mode, energy-counter persistence, connector direction, fuse, and backfeed paths.
2. S1Catalog and exact-MPN provenance. Every power monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review measurement uncertainty, timebase error, transient capture, common-mode limits, shunt heating, calibration, counter rollover, and source/load ground semantics.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Multiplying separately sampled voltage and current can mismeasure pulsed loads, and a backpowered monitor can energize a supposedly disconnected load.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep DC and pulsed loads with traceable references, compare accumulated energy over time, temperature-cycle the shunt/divider, and test disconnect/backfeed states.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse mains, billing/revenue claims, high-energy packs, load switching, converters, or ranges above the envelope.
• Do not infer dynamic accuracy, calibration, or counter retention from a clean schematic and DRC.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.