Vibecode a USB Power Monitor PCB with AI and Gate Checks

MakeIRL's generator treats a USB power monitor prompt as a self-contained project board. Current status: needs clarification.

A power-only USB monitor within 5 V and 2 A may fit with verified connector and measurement blocks. USB PD, data pass-through, host sourcing, and high-speed transparency are outside current support.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Connector genders/roles, current direction, 5 V-only versus PD, source/sink CC behavior, data pass-through, and cable assumptions
2. Range, shunt burden, common mode, monitor block, accuracy, sample rate, display/reporting, and calibration
3. ESD/shell grounding, connector anchoring, fuse/protection, enclosure, heat, and backfeed behavior

Block plan:

• Cataloged controller/module carrier
• Verified 5 V/2 A Kelvin current-monitor block
• Separate verified upstream/downstream USB-C power-only role blocks; the current single sink block is insufficient for inline behavior

Interfaces: USB-C power-only upstream/downstream, I²C measurement, UART/I²C reporting. Power plan: 5 V only and at most 2 A, with shunt, copper, connector, and cable drop included; no PD negotiation or sourcing invention.

• Anchor both connectors, keep the VBUS force path broad and Kelvin sense local, route CC independently for each role, and maintain short ESD/shell returns.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify upstream/downstream role and CC networks, no unintended data pins, shunt force/sense, connector orientation, VBUS path, backfeed, ESD, and total dissipation.
2. S1Catalog and exact-MPN provenance. Every USB power monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review USB-C role semantics, cable/e-marker limits, voltage drop, connector heat, shell/chassis ground, shunt error, backfeed, and user-facing claims.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Copying one sink receptacle circuit to both ends does not make a transparent inline power path and can create invalid CC presentation.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Test both plug orientations and cable combinations, sweep load to 2 A, measure insertion drop/heat and accuracy, and verify attach/detach/backfeed behavior.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse USB PD, charging protocols, source design, data transparency, USB high-speed, or current above 2 A.
• The current checked USB-C seed is a sink power input, not a ready-made inline monitor interface.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.