Vibecode a USB Gadget PCB with AI: USB-C and Gate Checks

MakeIRL's generator treats a USB gadget prompt as a self-contained project board. Current status: needs clarification.

The current checked USB-C block is power-only. A data gadget needs a verified USB-device/controller block and supported routing; high-speed modes are explicitly refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. USB device/host role, Full-Speed or other speed, exact controller block, descriptors/firmware path, and bus current
2. Receptacle MPN, CC topology, ESD, shell strategy, VBUS protection, and attach behavior
3. Board edge and enclosure, connector anchoring, pair geometry/stackup, programming, and test points

Block plan:

• Cataloged USB-capable controller or module carrier; current ESP32-C3 seed is not a generic native-USB block
• Current USB-C power block only for power; a separately verified data-capable connector block is required
• Verified programming, status, and optional low-speed peripheral blocks

Interfaces: USB 2.0 Full-Speed only when supported, GPIO/I²C/UART peripherals, SWD/JTAG/UART programming as appropriate. Power plan: USB VBUS within declared sink current, cataloged 3.3 V regulation, controlled inrush, and no unrequested source/PD behavior.

• Anchor the connector at the edge, put ESD at the entry, route D+/D− together over a continuous reference with minimal stubs, and keep crystal/clock loops compact.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Require two independent CC pulldowns for a sink, correct D+/D− pins in both receptacle rows, VBUS/shell protection, pair continuity, and controller USB pin parity.
2. S1Catalog and exact-MPN provenance. Every USB gadget block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review USB role and current advertisement, ESD return, connector shell mechanics, actual stackup geometry, oscillator requirements, firmware recovery, and host compatibility.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A power-only USB-C block can power a board but cannot enumerate, while one shared CC resistor creates orientation-dependent failure.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Test both plug orientations across several cables and hosts, enumeration, suspend/resume, inrush/current, firmware recovery, and ESD; inspect signal quality if needed.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse USB high-speed, USB PD negotiation, host sourcing, or invented controller/connector blocks.
• Do not silently turn a power-only seed into a data-capable topology because the prompt says 'USB gadget'.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.