Vibecode a Macropad PCB with AI: Gated Board Design Guide

MakeIRL's generator treats a macropad prompt as a self-contained project board. Current status: in envelope needs block.

A simple low-voltage matrix is conceptually inside the intended envelope, but the current catalog lacks switch-matrix, key-diode, and USB-HID blocks, so V2 must refuse rather than improvise them.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact switch and hot-swap footprint, 4×3 matrix map, diode direction, and encoder pinout
2. Controller/module choice, USB role, boot/programming path, and firmware matrix convention
3. Plate/case datum, switch spacing, mounting holes, connector face, height zones, and test pads

Block plan:

• Cataloged MCU/module carrier with boot, reset, decoupling, and programming evidence
• Verified key-matrix/diode and optional encoder blocks with deterministic row/column allocation
• Power-only or USB-device block only when its connector, CC, ESD, and data topology are supported

Interfaces: GPIO row/column matrix, quadrature GPIO encoder, USB HID or external module USB. Power plan: 5 V USB input and a cataloged 3.3 V rail within the 2 A envelope; LED budget and inrush must be explicit.

• Lock switch centers and plate cutouts first, keep diode/socket courtyards clear, route the matrix consistently, and mechanically anchor USB-C at the board edge.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Prove every switch closes one intended row/column path, every diode orientation matches firmware, USB-C has two CC pulldowns for a sink, and no matrix crossing is open or shorted.
2. S1Catalog and exact-MPN provenance. Every macropad block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review switch and socket mechanics, plate alignment, USB shell anchoring, ESD return, diode marks, boot access, and whether firmware can recover a blank controller.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A correct-looking matrix can ghost or lose an entire row when diode direction, connector view, or firmware row/column assignment differs from the schematic.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Continuity-scan every key before fitting switches, then test simultaneous chords, encoder direction, USB enumeration in both plug orientations, and all status outputs.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse unsupported USB high-speed, wireless, battery charging, or invented hot-swap/socket footprints.
• Ask for clarification or refuse if switch standard, plate geometry, controller, current, or connector role is missing.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.