Generate an RP2040 Carrier Board with AI: Scope and Gates

MakeIRL's generator treats a RP2040 carrier prompt as a module carrier. Current status: in envelope needs block.

RP2040 is named in the intended roadmap but has no current catalog block. A bare-chip design needs exact flash, clock, USB, regulator/decoupling, boot and layout evidence and is refused today.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact RP2040 package, QSPI flash MPN/capacity, crystal or clock, USB role/connector, boot/reset, SWD, firmware, and GPIO assignment
2. 3.3 V source, internal-core decoupling and regulator requirements, current peaks, flash/clock layout constraints, ESD, and grounding
3. Board outline, USB face, crystal/flash placement zone, mounting, test points, enclosure, assembly capability, and block verification plan

Block plan:

• Future verified RP2040 + exact flash + clock + decoupling minimal block
• Future verified USB-C data/power/ESD and SWD/BOOTSEL blocks
• Only cataloged low-speed peripheral blocks within the envelope

Interfaces: QSPI internal flash, USB Full-Speed, SWD and low-speed GPIO/I²C/UART/SPI. Power plan: Verified 3.3 V input under the envelope with all RP2040 core/IO decoupling and USB current budget; no invented SMPS.

• Keep flash and clock nets tightly constrained, place decouplers at each supply, preserve USB return, and expose SWD/BOOTSEL without GPIO conflicts.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Future checks must prove exact flash/clock pinout and parts, RP2040 supplies/decoupling, USB D+/D−/CC/ESD, BOOTSEL, SWD, and package pad map.
2. S1Catalog and exact-MPN provenance. Every RP2040 carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review RP2040 hardware design guidance, flash and crystal source truth, USB stackup, core/IO power, boot recovery, thermal, assembly, and physical tests.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• An RP2040 schematic can pass ERC with the wrong flash pinout, unsuitable crystal network, missing supply decoupling, or swapped USB data.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• A future block needs two-lot physical evidence: rail/clock, QSPI boot, SWD, USB enumeration and signal quality, GPIO, load/current, temperature, and recovery.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse RP2040 generation until the entire minimal-design block—not just the MCU symbol—is verified and cataloged.
• Do not substitute Raspberry Pi Pico carrier evidence for a bare RP2040 chip design.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.