Vibecode a Current Monitor PCB with AI: Kelvin Gate Guide

MakeIRL's generator treats a current monitor prompt as a self-contained project board. Current status: in envelope needs block.

A ≤12 V, ≤2 A monitor can fit once a verified shunt/amplifier or digital monitor block exists. The current catalog has no analogue current-sense block.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Current range and transients, bus/common-mode range, high/low side, direction, bandwidth, fault energy, and acceptable burden
2. Exact shunt and monitor MPN, gain/range, accuracy and temperature budget, address, alert, and calibration
3. Connector and copper path, isolation/grounding, test injection, enclosure heat, and external supply relationship

Block plan:

• Cataloged controller/module carrier
• Verified four-terminal shunt plus current-monitor block with exact range and common-mode evidence
• Protected force connectors and separate Kelvin sense routing block

Interfaces: I²C or verified analog output, alert GPIO, high-current force path plus Kelvin sense. Power plan: At most 12 V and 2 A through the board, with calculated shunt, copper, connector, via, and fuse loss.

• Route load current through full shunt terminals and take Kelvin traces from specified sense points, away from copper drops and switching fields.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Prove force/sense net separation, shunt value/power, monitor common-mode and input range, connector polarity, current-path necks, address, and alert state.
2. S1Catalog and exact-MPN provenance. Every current monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review burden voltage, shunt pulse and temperature coefficient, amplifier error, common-mode transients, fault energy, ground loops, and calibration.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Sense traces connected to load copper instead of Kelvin points measure PCB drop as current and produce temperature-dependent error.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep bidirectional or unidirectional current with a calibrated load, map gain/offset/temperature, pulse within rating, and compare force versus sense voltage.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse above 12 V/2 A, mains, uncataloged shunts/amplifiers, isolation design, or safety/protection claims.
• Require a numerical accuracy and burden budget; 'measure current accurately' is not a complete requirement.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.