Vibecode a Battery Monitor PCB with AI: Limits and Gates

MakeIRL's generator treats a battery monitor prompt as a self-contained project board. Current status: needs clarification.

Monitoring a protected external battery up to 12 V may fit with a verified measurement block. Lithium charging, balancing, protection design, and direct cell management are refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Chemistry, series count, protected/unprotected status, nominal/maximum/transient voltage, source impedance, and fault energy
2. Voltage/current/temperature accuracy, gauge or ADC block, isolation/grounding, sample rate, sleep leakage, and calibration
3. Connector, fuse/sense protection, enclosure, cable length, test points, load relationship, and charging boundary

Block plan:

• Cataloged controller/module carrier
• Verified voltage/current measurement block rated for the exact external protected source
• Protected sense connector and low-voltage power block explicitly separated from any charger/protection function

Interfaces: I²C/ADC measurement, UART/I²C reporting, protected high-impedance sense. Power plan: Measure only an externally protected source at or below 12 V; keep monitor draw and divider leakage within budget and refuse charging.

• Separate source-energy entry from logic, put protection at the connector, use Kelvin sense where current is measured, and maintain intentional grounds.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify maximum voltage and resistor ratings, divider ratio and ADC range, shunt force/sense nets, connector polarity, fuse/protection, ground path, and no charging connection.
2. S1Catalog and exact-MPN provenance. Every battery monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review battery chemistry and protection ownership, fault energy, creepage, resistor pulse/voltage rating, shunt heat, isolation, calibration, and safe probing.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A divider sized for nominal battery voltage can overrange the ADC or exceed resistor voltage/pulse limits during charge and transients.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep safe source voltage/current with calibrated instruments, test reversed/open sense under controlled energy, measure error and heat, and verify monitor sleep draw.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse lithium charging, cell balancing, BMS/protection, packs above 12 V, sources above 2 A board current, or unknown chemistry.
• A monitor is not a charger or safety system and must not be marketed as one.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.