Head-to-head
MakeIRL vs JLC DFM: KiCad source gate or free gerber DFM check?
Choose JLC DFM when you are ordering from JLCPCB and want a free gerber-level DFM/DFA analysis matched to their process. Choose MakeIRL when you want a fab-neutral, paid preflight of the KiCad source itself — schematic ERC, layout DRC, schematic-to-PCB parity, and BOM lines checked against live distributor stock — before you even export gerbers.
They check different layers of the stack: JLC DFM analyzes exported gerbers against JLCPCB's manufacturing process, while MakeIRL gates the KiCad project (schematic + layout + BOM) before export. Many teams can sensibly use both.
Side by side
| MakeIRL | JLC DFM | |
|---|---|---|
| Maker | MakeIRL | JLCPCB |
| Price | $79 one-time per board release, no subscription (as of July 2026) | Free (as of July 2026) |
| Runs as | Online release gate; also runs from Claude Code / Cursor via MCP | Online web tool, nothing to download |
| Input files | Native KiCad source: .kicad_sch + .kicad_pcb | Gerber files uploaded as zip/rar, up to 50 MB |
| What it checks | ERC on the schematic, DRC on the layout, schematic ↔ PCB parity, BOM line completeness with MPN / package sanity and availability against live distributor stock, gerber / drill / placement export integrity, named heuristic checks (power, reset, programming, connector patterns) | DFM and DFA analysis across five modules — traces, solder mask, drilling, silkscreen, and component assembly — using a 30+ point checklist, plus BOM matching against JLCPCB's component library |
| How results arrive | Plain-English report with a BLOCKED / REVIEW / READY verdict; every report states explicitly that function is not proven | 2D/3D visualization in the browser and a downloadable PDF report |
| Fab tie-in | Fab-neutral — the preflight is not tied to any one factory's ordering pipeline | Built by JLCPCB and integrated with JLCPCB fabrication and assembly |
Competitor facts checked against JLCPCB’s public site as of July 2026. Pricing and capabilities can change — verify before you rely on them.
When JLC DFM is the better pick
You are ordering from JLCPCB and want a free pre-check aligned to their process, including BOM matching against their parts library.
It is free (as of July 2026), so if a gerber-level check is all you need, there is no cost to trying it.
When MakeIRL is the better pick
You want one gate over the whole KiCad project before gerbers exist: ERC on the schematic, DRC on the layout, schematic ↔ PCB parity, and BOM lines checked against live distributor stock. It costs $79 one-time per board release (as of July 2026) and is fab-neutral.
Honest limits: KiCad projects only, it costs money while fab-side checkers are free, and it does not replace the manufacturer's own DFM review before production. When every check passes, the report reads “READY FOR MANUFACTURING — function not proven” — no automated check can prove a circuit does what you meant.
Frequently asked questions
Is JLC DFM free?
Yes. JLCPCB describes it as a free online DFM tool (as of July 2026). MakeIRL's automated preflight is $79 one-time per board release.
Does JLC DFM check my schematic?
JLC DFM analyzes uploaded gerber files (zip/rar, up to 50 MB) plus BOM matching against JLCPCB's library. It does not take KiCad schematic source. MakeIRL runs ERC on the .kicad_sch and checks schematic-to-PCB parity, which requires the KiCad project files.
Does either tool prove my circuit works?
No. Neither a gerber DFM check nor MakeIRL's preflight can prove functional correctness. MakeIRL's passing verdict reads “READY FOR MANUFACTURING — function not proven”, and that limitation applies to every automated checker in this comparison.