Generate an STM32G0 Carrier Board with AI: Scope Design Guide

MakeIRL's generator treats a STM32G0 carrier prompt as a module carrier. Current status: in envelope needs block.

The STM32G0 family contains many packages and peripheral variants; no current catalog block exists. The exact MPN, clock, boot, power and interface topology must be verified first.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact STM32G0 MPN/package/revision, peripherals and pins, internal/external clock, reset/BOOT0, SWD, firmware, and option bytes
2. VDD/VDDA range and filtering, all decoupling, current, analogue reference, USB/UART connector/protection, and ground strategy
3. Board outline, connector faces, clock and bypass zones, mounting, programming fixture, enclosure, assembly, and verification plan

Block plan:

• Future verified exact-MPN STM32G0 minimal block
• Verified SWD/reset/boot and optional exact-interface blocks
• Cataloged USB power and low-speed peripheral blocks only when pin/peripheral compatibility is proven

Interfaces: SWD, UART/I²C/slow SPI/GPIO, USB only on an exact supporting MPN and verified block. Power plan: Verified 3.3 V rail under the envelope with separate analogue supply/reference treatment where the exact device requires it.

• Place every supply decoupler at its pin group, keep VDDA/reference quiet, choose clock placement deliberately, and preserve SWD/reset/boot recovery.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Future checks must bind the exact MPN to package pads/peripherals, verify all supply pins and decouplers, VDDA, clock, reset/BOOT0, SWD, and interface voltage.
2. S1Catalog and exact-MPN provenance. Every STM32G0 carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review datasheet/reference manual/errata, alternate-function mapping, option bytes, clock accuracy, analogue supply, debug recovery, USB capability, and assembly.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Selecting pins from another STM32G0 suffix can assign a peripheral that is absent or on a different pad while the family name still looks correct.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• A future block needs rail/current, clock, reset/boot, SWD and recovery, every declared peripheral, analogue accuracy where used, temperature, and lot evidence.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse family-only requests, invented alternate functions, unknown packages, unsupported USB, or an uncataloged minimal block.
• Exact orderable MPN and package are required before pin allocation begins.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.