Vibecode a Debug Adapter PCB with AI: Pinout Gate Guide

MakeIRL's generator treats a debug adapter prompt as a self-contained project board. Current status: in envelope needs block.

A passive or low-speed buffered adapter can fit once both connector maps and any level/protection block are cataloged. MakeIRL must refuse an inferred pinout.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact debugger and target connector MPNs, top/mating views, pin maps, key, cable orientation, and ground pins
2. Protocol, voltage range, direction, speed, series resistors/buffers, reset, VTref, target-power and protection policy
3. Board edge, shroud/latch/cable envelopes, labels, mounting, strain, probe loops, and continuity test

Block plan:

• Verified connector-footprint and pin-map blocks for both ends
• Passive map block or verified level/buffer/protection block
• Optional cataloged status or power-detect block without target sourcing

Interfaces: SWD/JTAG/UART or another declared low-speed debug bus, VTref sensing, ground and reset. Power plan: Default to target-voltage sensing only; any target power output requires a separate current-limited verified block and explicit permission.

• Honor mating-view pin maps, keep clocks and returns close, key both ends, label from the user's view, and give cables mechanical clearance.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Machine-compare both pin maps, verify no target-power short, VTref direction, ground coverage, reset, buffer direction/enable, and connector pin one.
2. S1Catalog and exact-MPN provenance. Every debug adapter block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review voltage compatibility, whether the debugger drives target power, cable mirroring, protocol edge rate, reset/boot side effects, and accidental hot-plug states.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A connector viewed from the cable side can mirror every debug signal while its keyed housing still mates perfectly.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Continuity-map every pin with no target attached, test isolation/power policy, then connect a current-limited known target and exercise programming, reset, and recovery.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse guessed pinouts, proprietary unknown connectors, high-speed interfaces, target power without limits, or voltage levels outside catalog evidence.
• A debug name such as '10-pin SWD' is not enough; exact connector/view conventions are required.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.