Vibecode a Prototyping Breakout PCB with AI and Gate Checks

MakeIRL's generator treats a prototyping breakout prompt as a self-contained project board. Current status: in envelope needs block.

A passive breakout is a strong constrained use case once the exact module/connector footprint and pin map are in the catalog. Unknown modules are refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact module/connector MPN, package drawing, top/mating view, pin numbers, voltage domains, reserved and no-connect pins
2. Header/socket series, row pitch/spacing, breadboard gap, pin ordering, duplicated rails, and protection or level shifting
3. Board outline, mounting, silkscreen labels, component clearance, insertion force, test points, and assembly side

Block plan:

• Verified source module/connector footprint and pin-map block
• Verified destination header/socket block
• Optional verified protection, level-shift, decoupling, or regulator blocks only when requested and in envelope

Interfaces: direct low-speed pin breakout, power/ground rails, optional I²C/UART/GPIO through declared blocks. Power plan: Passive by default; any supplied rail must have explicit source, voltage, current, reverse/backfeed behavior, and cataloged protection.

• Set both connector grids from mechanical drawings, route pins monotonically when possible, keep labels visible after mating, and avoid board-edge breadboard collisions.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Compare every source pad to destination pin, no-connect/reserved handling, voltage-domain labels, duplicated ground, header pitch, finished holes, and top/bottom view.
2. S1Catalog and exact-MPN provenance. Every prototyping breakout block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review module orientation, solder side, mating parts, breadboard fit, backfeed, voltage tolerance, mechanical support, and whether labels remain unambiguous.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A breakout can be electrically one-to-one yet unusable because row spacing misses the breadboard gap or numbering is mirrored from the bottom view.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Continuity-map all pins, insulation-test adjacent rails as appropriate, mate real headers/module/breadboard, and verify any optional protection or level shifting.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse unknown module drawings or pinouts and do not infer voltage tolerance from a connector label.
• Do not add a regulator, level shifter, or protection network unless its exact block and direction are supported.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.