Vibecode an Audio Level Meter PCB with AI and Gate Checks

MakeIRL's generator treats a audio level meter prompt as a self-contained project board. Current status: in envelope needs block.

The low-voltage display/controller portion can fit, but the current catalog lacks verified audio input, bias, rectifier/ADC, and level-display blocks. V2 must refuse the analog topology today.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Source level/impedance, balanced or unbalanced input, bandwidth, overload, connector, ground relationship, and protection
2. Meter standard and ballistics, ADC/front-end block, LED/display range, update rate, calibration, and clipping indication
3. USB power/noise, enclosure and jack mechanics, channel count, test injection point, and acceptable accuracy

Block plan:

• Cataloged controller/module carrier
• Verified line-input protection/bias/ADC block with measured noise and range
• Verified low-current display/driver and USB power blocks

Interfaces: verified analog input, ADC/I²C/SPI data, GPIO or serial display. Power plan: USB-derived low-voltage rails with analogue filtering; no generated bipolar, boost, microphone phantom, or high-power LED supply.

• Keep input and reference returns away from LED scan and USB current, place protection at the jack, and preserve channel and chassis grounding intent.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check input protection and bias, coupling polarity, ADC range/reference, display current limit, connector sleeve/ring/tip map, and analogue/digital return path.
2. S1Catalog and exact-MPN provenance. Every audio level meter block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review gain/error budget, source compatibility, noise, grounding, anti-alias filtering, display ballistics, jack mechanics, and calibration traceability.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• An LED meter can display stable numbers while clipping its front end, loading the source, or measuring USB and scan noise instead of audio.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep level and frequency, measure threshold error, clipping, noise floor, crosstalk and display current, then test multiple source/ground configurations.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse microphone preamps, phantom power, mains audio, invented precision analog, or unsupported display drivers.
• Do not claim studio accuracy, safety, or audio quality without measured analogue validation.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.