Vibecode an Analog Control Panel PCB with AI and Gate Checks

MakeIRL's generator treats a analog control panel prompt as a self-contained project board. Current status: in envelope needs block.

The mechanical low-speed concept fits the intended envelope, but V2 currently lacks verified potentiometer, ADC, protection, and panel-control blocks.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Pot/switch MPNs, resistance/taper, angle/travel, wiper failure behavior, voltage range, filter, and required resolution
2. ADC/reference block, channel count, source impedance, sample rate, calibration, digital interface, and noise target
3. Panel datum, shaft/bushing, knob, control spacing/height, mounting, connector, labels, and enclosure

Block plan:

• Cataloged controller/module carrier
• Verified potentiometer protection/filter and ADC/reference blocks
• Verified buttons, status, Qwiic/USB power, and programming blocks

Interfaces: verified ADC analogue inputs, GPIO buttons, I²C/Qwiic data. Power plan: USB-derived 3.3 V reference/logic within the envelope; no generated bipolar rails or external analogue drive.

• Reference every control to one panel datum, keep LED/USB digital returns away from the ADC reference, and make wiper protection/filtering local.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check pot pin/wiper maps, ADC range/reference and source impedance, RC values, button pulls, panel footprints, and analogue/digital return connectivity.
2. S1Catalog and exact-MPN provenance. Every analog control panel block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review error/noise budget, wiper open behavior, ESD at user controls, mechanical tolerances, calibration, control feel, and firmware mapping.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A potentiometer footprint can fit while its wiper and end terminals are swapped, reversing control direction or shorting a rail at an endpoint.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep all controls through endpoints, measure codes, noise, linearity and crosstalk, test open wipers/buttons, and fit knobs/panel across tolerances.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse precision analogue claims, bipolar/high-voltage controls, unknown pot footprints, or unsupported ADC/reference topology.
• A clean digital carrier does not prove analogue resolution, calibration, or panel mechanics.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.