Vibecode a Lab Control Panel PCB with AI and Gate Checks

MakeIRL's generator treats a lab control panel prompt as a self-contained project board. Current status: needs clarification.

A USB-powered human-interface panel can fit with verified controls/display blocks. Direct instrument, mains, high-voltage, safety interlock, or high-current control is refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Controls/display MPNs, interface and voltage, indicators, emergency or interlock semantics, firmware, and safe startup state
2. External equipment interface, isolation/grounding, cable and connector, voltage/current direction, ESD, and fault behavior
3. Panel datum, control heights, labels, mounting, enclosure, service access, and test sequence

Block plan:

• Cataloged controller/module carrier
• Verified encoder/button/status/display interface blocks
• Verified low-voltage keyed communication and USB power blocks; no direct hazardous control

Interfaces: GPIO human inputs, I²C/slow SPI display, low-voltage UART/I²C output. Power plan: USB-only interface power; external equipment control must be low-voltage, bounded, and cataloged, with no high-energy output.

• Lock the panel datum, group controls by function, isolate user-cable ESD at entry, and preserve accessible programming and test points.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify every control/display/connector pin, default and interlock states, voltage direction, no backfeed, ESD, labels, and the absence of hazardous output paths.
2. S1Catalog and exact-MPN provenance. Every lab control panel block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review human factors, interlock meaning, emergency behavior, equipment grounding, connector misuse, firmware recovery, ESD, labels, and failure containment.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Calling a button an interlock does not create an independent safety function; generated firmware and a GPIO cannot be the sole hazardous-energy barrier.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Exercise every input/output and display state, disconnect/reverse cables safely, reset during commands, test ESD, and fit the complete panel/enclosure.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse mains, high voltage/current, lasers, heaters, motors, safety-critical interlocks, or unknown instrument interfaces.
• Offer only a bounded low-voltage user interface, not autonomous laboratory equipment control.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.