SOIC-14 PCB Footprint: Dimensions, DFM, and Assembly Guide

SOIC-14 is a gull wing package used for surface mount assembly, also seen labeled SO-14, narrow SOIC-14, JEDEC MS-012 AB. A dependable footprint follows the exact orderable-device drawing rather than the family name: nominal body 3.9 × 8.7 mm nominal, overall span About 6.0 mm lead span, seated height Typically 1.35–1.75 mm, pitch 1.27 mm, pin count 14, and exposed pad None on the standard outline.

Use the selected package drawing and keep the 3.9 mm narrow body distinct from wider SO families.

Typical uses include quad op-amps, logic gates, analog switches. A narrow 3.9 mm SOIC-14 commonly follows JEDEC MS-012; lead length and body tolerances still come from the exact part.

• Seven leads per side extend the body to roughly 8.7 mm; pitch error accumulates along the row, so a hand-drawn footprint is less forgiving than SOIC-8.
• Gull-wing package names cover families of drawings; body width, lead span, lead length, and seated height must all match the orderable part.

Fan power and ground directly to the relevant units, place local bypassing near supply pins, and avoid long shared return paths on multi-channel analog parts.

• Route away from the lead toe, preserve visible solder fillets, and keep the pin-one cue unambiguous on copper, silkscreen, and the assembly drawing.

Hand assembly is rated easy. Fluxed drag soldering or stencil reflow. Watch for a 180-degree rotation on the nearly symmetric long body.

• Use matched pad rows and paste apertures across the long package so cumulative placement skew does not leave an end lead short of its land.
• Use symmetric paste apertures and a real component courtyard so placement does not rotate or crowd neighboring parts.
• Do not lengthen every pad for hand soldering on the production footprint; excessive toe extension consumes routing and can increase solder movement.

Inspection focus:

• Inspect both end leads first for row registration, then scan all inner joints for bridges and verify the pin-one mark against the assembly drawing.
• All lead toes should be optically accessible. Inspect alignment, heel/toe wetting, bridges, lifted leads, and orientation before functional test.

Common mistakes:

• Using a 14-pin symbol with hidden power units can leave supply pins unconnected even though every visible logic or op-amp unit looks complete.
• Never infer functional pin numbering from another IC in the same mechanical family; verify symbol, footprint, and datasheet together.

1. Before approving SOIC-14, compare the exact orderable-device drawing with the library item: body range (3.9 × 8.7 mm nominal), terminal or lead span (About 6.0 mm lead span), pitch (1.27 mm), pin count (14), height (Typically 1.35–1.75 mm), and exposed-pad definition (None on the standard outline). Record the source drawing revision and every intentional courtyard, toe, heel, side, mask, or paste adjustment.
2. Treat the easy hand-solder rating as a prototype-planning input, not proof of production yield. Review a 180-degree rotation on the nearly symmetric long body with the assembler, confirm that fluxed drag soldering or stencil reflow is compatible with the build, and require the S1 connectivity gate plus relevant S2 geometry checks to pass against the released footprint and selected fabrication profile.

Manufacturing gate checks:

1. S1Pad count, numbering, and schematic parity. Schematic parity must include hidden or multi-unit power pins and confirm all fourteen pads are present in the expected numbering order.
2. S2Lead-to-pad alignment and solder-mask web. Pitch, toe extension, and mask slivers must fit the selected assembly capability without hiding a lead.
3. S2Courtyard and body clearance. The body, leads, placement tolerance, rework access, and nearby height limits all belong in the manufacturing review.