SOIC-8 PCB Footprint: Dimensions, DFM, and Assembly Guide

SOIC-8 is a gull wing package used for surface mount assembly, also seen labeled SO-8, narrow SOIC, JEDEC MS-012 AA. A dependable footprint follows the exact orderable-device drawing rather than the family name: nominal body 3.9 × 4.9 mm nominal, overall span About 6.0 mm lead span, seated height Typically 1.35–1.75 mm, pitch 1.27 mm, pin count 8, and exposed pad None on standard SOIC-8; exposed-pad variants are separate.

Use the exact MS-012 variant or manufacturer drawing; PowerPAD and wide-body parts need different footprints.

Typical uses include op-amps, serial memories, gate drivers. The common narrow SOIC-8 follows a 3.9 mm body and 1.27 mm pitch, but the exact JEDEC variant and MPN drawing control.

• Four leads per side at 1.27 mm pitch make SOIC-8 forgiving, but the 3.9 mm body width must not be confused with 5.3 mm or wide-body isolation packages.
• Gull-wing package names cover families of drawings; body width, lead span, lead length, and seated height must all match the orderable part.

Place bypass capacitors beside the actual supply pins, and keep op-amp inputs or switch-node loops short according to the circuit rather than the generous lead pitch.

• Route away from the lead toe, preserve visible solder fillets, and keep the pin-one cue unambiguous on copper, silkscreen, and the assembly drawing.

Hand assembly is rated easy. Drag solder with flux or ordinary stencil reflow. Watch for confusing narrow, wide, and exposed-pad so-8 variants.

• Provide a clear pin-one cue outside the body and enough toe extension for inspection without making a universal oversized hand-solder footprint.
• Use symmetric paste apertures and a real component courtyard so placement does not rotate or crowd neighboring parts.
• Do not lengthen every pad for hand soldering on the production footprint; excessive toe extension consumes routing and can increase solder movement.

Inspection focus:

• All eight joints are visible; inspect for bridges at the heels, lifted leads, rotated placement, and the correct top mark before power-up.
• All lead toes should be optically accessible. Inspect alignment, heel/toe wetting, bridges, lifted leads, and orientation before functional test.

Common mistakes:

• Dropping an exposed-pad SOIC-8 power IC onto a plain eight-pad footprint removes its specified thermal and often electrical connection.
• Never infer functional pin numbering from another IC in the same mechanical family; verify symbol, footprint, and datasheet together.

1. Before approving SOIC-8, compare the exact orderable-device drawing with the library item: body range (3.9 × 4.9 mm nominal), terminal or lead span (About 6.0 mm lead span), pitch (1.27 mm), pin count (8), height (Typically 1.35–1.75 mm), and exposed-pad definition (None on standard SOIC-8; exposed-pad variants are separate). Record the source drawing revision and every intentional courtyard, toe, heel, side, mask, or paste adjustment.
2. Treat the easy hand-solder rating as a prototype-planning input, not proof of production yield. Review confusing narrow, wide, and exposed-pad so-8 variants with the assembler, confirm that drag solder with flux or ordinary stencil reflow is compatible with the build, and require the S1 connectivity gate plus relevant S2 geometry checks to pass against the released footprint and selected fabrication profile.

Manufacturing gate checks:

1. S1Pad count, numbering, and schematic parity. The gate must distinguish ordinary SOIC-8 from wide-body and exposed-pad variants and preserve the exact symbol pin map.
2. S2Lead-to-pad alignment and solder-mask web. Pitch, toe extension, and mask slivers must fit the selected assembly capability without hiding a lead.
3. S2Courtyard and body clearance. The body, leads, placement tolerance, rework access, and nearby height limits all belong in the manufacturing review.