Vibecode a Rotary Controller PCB with AI and Gate Checks

MakeIRL's generator treats a rotary controller prompt as a self-contained project board. Current status: in envelope needs block.

A low-speed encoder/button carrier is inside the intended envelope after verified encoder and optional LED blocks exist. The current seed catalog lacks them.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Encoder MPN, mechanical versus magnetic type, quadrature pinout, detents/pulses, switch, pulls, debounce, and maximum rotation rate
2. Controller/module, HID/MIDI/serial role, LED ring count/current, startup behavior, programming, and firmware convention
3. Panel datum, shaft/bushing/knob, anti-rotation feature, enclosure, mounting, connector face, and cycle target

Block plan:

• Cataloged controller/module carrier
• Verified encoder/switch/debounce block
• Verified low-current LED/status and USB power blocks

Interfaces: quadrature GPIO, push-button GPIO, optional low-speed LED/I²C. Power plan: USB-derived low-voltage rail with explicit LED budget; no battery, motorized encoder, or high-current lighting.

• Reference the shaft and anti-rotation feature to the panel, support mechanical torque, keep encoder signals away from LED scan returns, and expose test pads.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify encoder A/B/common and switch map, pull states, boot conflicts, debounce, LED current limiting, panel footprint, and connector/power nets.
2. S1Catalog and exact-MPN provenance. Every rotary controller block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review mechanical cycle/torque, detent-to-pulse convention, firmware direction, contact bounce, panel stack, knob clearance, ESD, and tactile feel.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Swapped A/B channels reverse direction, while an encoder footprint with the right pin count can still place locating tabs or shaft off the panel datum.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Rotate at slow/fast rates both directions, press while turning, log missed/extra counts and bounce, test LED current, and cycle the real knob/panel assembly.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse motorized encoders, haptics, wireless/battery requests, or an unknown mechanical footprint.
• A generic 'rotary encoder' prompt lacks the detent, pulse, pin, and panel data needed for a real board.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.