Vibecode a Water Leak Detector PCB with AI and Gate Checks

MakeIRL's generator treats a water leak detector prompt as a self-contained project board. Current status: in envelope needs block.

A carrier for a cataloged dry-contact or digital leak probe could fit. The current catalog lacks probe and low-leakage input blocks, so it must not generate electrode chemistry or thresholds.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Probe type/material, wet/dry resistance, cable length, excitation waveform, corrosion target, and replacement interval
2. Alarm behavior, latching/reset, fail-safe open-wire detection, output load, power source, and communications
3. Wet/dry boundary, coating and drainage, connector strain relief, enclosure, cleaning, and test method

Block plan:

• Cataloged controller/module carrier
• Verified dry-contact or AC-excited leak-input block with cable protection
• Cataloged power, alarm-interface, connector, and status blocks

Interfaces: protected GPIO or verified low-leakage input, alarm GPIO, optional I²C/UART reporting. Power plan: Low-voltage SELV sensing with limited probe energy; external alarm loads must stay inside verified block/current limits.

• Keep wet-side copper separated, make leakage paths long and clean, put surge/ESD protection at the cable, and route drainage away from electronics.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify probe connector polarity, input protection, pull/threshold values, open-wire behavior, coating exclusions, and no DC electrode bias beyond the approved block.
2. S1Catalog and exact-MPN provenance. Every water leak detector block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review corrosion, false alarms from condensation/contamination, cable common mode, fail-safe semantics, alarm audibility, ingress, and maintenance.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A high-value pull resistor plus flux residue can look like a wet probe, while continuous DC across exposed electrodes accelerates corrosion.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Wet and dry the real probe repeatedly with representative water, contamination, and cable length; test open/short cable, drying time, alarm latch, and leakage drift.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse mains pumps/valves, safety guarantees, unknown electrode materials, lithium backup, or invented precision front ends.
• A generated alarm carrier is not proof of waterproofing, corrosion life, or property-protection reliability.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.