Vibecode a Soil Sensor PCB with AI: Corrosion and Gates

MakeIRL's generator treats a soil sensor prompt as a self-contained project board. Current status: in envelope needs block.

A low-voltage carrier for an external digital soil-sensor module can fit after that module is cataloged. MakeIRL must not invent exposed electrodes, analog front ends, or corrosion lifetime.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. External module/connector or exact electrode material and geometry, measurement topology, frequency, and range
2. Soil chemistry, immersion, cable length, leakage, sealing/coating boundary, and expected field life
3. Power source, sample duty, calibration references, enclosure, strain relief, and replacement plan

Block plan:

• Cataloged controller/module carrier
• Verified external digital soil-sensor interface or separately verified analog/electrode block
• Protected connector, USB power, and coating-boundary blocks where applicable

Interfaces: I²C or low-speed digital module, optional ADC only through a verified analog block, keyed field connector. Power plan: Low-voltage, low-current excitation and USB/catalog power; no battery charging or invented bipolar/boost supply.

• Keep leakage-sensitive nodes clean and guarded, separate wet electrode territory from electronics, and give the cable a real mechanical and moisture boundary.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify connector pinout, excitation never applies DC when prohibited, coating/keepout geometry, no leakage shortcuts, voltage compatibility, and exact sensor-block identity.
2. S1Catalog and exact-MPN provenance. Every soil sensor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review electrode chemistry, electrolysis/corrosion, contamination, ingress, cable capacitance, analog error budget, calibration, and field replacement.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• Bare copper or ordinary ENIG in wet soil can corrode and drift, while a cup-of-water result says little about soil type, salts, aging, or sealing.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Compare multiple soil types and moisture levels, wet/dry cycle the probe, log drift, inspect corrosion and leakage, and test cable/seal strain.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse invented electrode lifetime, unsafe chemistry claims, uncataloged precision analog, or battery charging.
• An external-module carrier does not validate the external probe's calibration, corrosion resistance, or waterproofing.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.