Generate a Voltage Regulator Carrier with AI: Scope Guide

MakeIRL's generator treats a voltage regulator carrier prompt as a module carrier. Current status: needs clarification.

A verified low-current LDO block within 12 V/2 A could fit. The current AP2112K exists only inside the checked USB power block; switch-mode conversion is explicitly refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact regulator MPN/package, input min/max/transients, output/tolerance, load profile, dropout, quiescent current, enable, and fault behavior
2. Required capacitor values/ESR/bias/rating, stability, dissipation, junction limit, copper assumptions, and reverse-current behavior
3. Connectors, polarity/protection, heat-spreading area, enclosure ambient, mounting, test load, and approved alternatives

Block plan:

• Verified exact LDO topology including required capacitors and enable state
• Verified protected input/output connector blocks
• Optional monitoring/status block; no SMPS, inductor, charge pump, or invented substitution

Interfaces: DC input, regulated DC output, optional enable/status GPIO. Power plan: At most 12 V input and 2 A envelope, but actual LDO output is limited by dropout dissipation and verified block rating, often far lower.

• Place capacitors at their pins, keep ground/feedback clean, spread heat from the correct tab/pad net, and separate input/output connectors.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check pin and tab map, input/output capacitor exact ratings, enable default, maximum dissipation, reverse paths, connector polarity, thermal pad, and current copper.
2. S1Catalog and exact-MPN provenance. Every voltage regulator carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review stability, capacitor derating, dropout, startup, reverse current, safe operating area, thermal resistance, load transients, short behavior, and enclosure.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A regulator advertised for high current can overheat at a modest load when the input-output drop and board copper make package dissipation the limit.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep input and load, measure output/ripple/dropout, startup and transients, short/reverse states where allowed, and case/board temperature at worst ambient.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse switch-mode regulators, charge pumps, negative/bipolar rails, high-energy sources, or uncataloged LDO substitutions.
• Do not use the AP2112K seed as a universal regulator block outside its checked USB-power topology.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.