Vibecode a Synth Control Surface PCB with AI and Gate Checks

MakeIRL's generator treats a synth control surface prompt as a self-contained project board. Current status: in envelope needs block.

Digital controls are conceptually in envelope, but calibrated CV inputs/outputs need verified analogue/reference blocks absent from the current catalog. Bipolar rails are not generated.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Digital-only or CV/audio scope, exact voltage ranges, source/load impedance, accuracy, protection, calibration, grounding, and rail requirements
2. Control/jack MPNs, ADC/DAC/reference blocks, MIDI, display/LED, firmware map, and startup behavior
3. Panel datum, control and jack heights, knobs, mounting, labels, enclosure, cable access, and test/calibration points

Block plan:

• Cataloged controller/module carrier
• Verified human-control and MIDI blocks for a digital-only surface
• CV/ADC/DAC/reference blocks only after separate verification; no invented bipolar supply

Interfaces: GPIO/ADC controls, MIDI through verified block, CV only through verified analogue blocks. Power plan: Current safe path is USB-powered digital control; bipolar or modular-synth rails require unsupported power/analogue blocks.

• Reference all controls to the panel, separate LED/digital returns from analog references, protect jacks at entry, and keep calibration access.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify control and jack pin maps, ADC/DAC range, reference and rail nets, output protection, MIDI mapping, LED current, and panel geometry.
2. S1Catalog and exact-MPN provenance. Every synth control surface block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review CV standards, accuracy and temperature, op-amp headroom, output faults, grounding, audio interaction, panel tolerance, calibration, and musical workflow.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A nominal 0–5 V output can clip or be damaged when patched into bipolar or differently grounded modular equipment.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• For digital scope, test every control/MIDI event; for future verified CV blocks, calibrate gain/offset, sweep loads, faults, temperature, noise, and crosstalk.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse invented CV/audio analogue, bipolar/eurorack power, unknown jacks, or precision claims without verified blocks.
• Offer a digital control surface when analogue requirements exceed the generator rather than silently simplifying them.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.