Vibecode a Surge Monitor PCB with AI: Refusal and Limits

MakeIRL's generator treats a surge monitor prompt as a self-contained project board. Current status: refused.

Surge capture/protection involves high transient energy, specialized front ends, spacing, isolation, and standards. It is outside V2. Only a cataloged isolated low-energy event input could change that.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Surge standard/waveform, voltage/current/source impedance, repetition, domain, common mode, energy, and measurement bandwidth
2. External certified detector or probe output, isolation evidence, logic levels, pulse width/rate, connector, and fail-safe state
3. Lab safety boundary, enclosure, creepage, protective earth, instruments, qualified reviewer, and destructive test plan

Block plan:

• No surge front-end, TVS network, divider, isolation barrier, or high-energy connector is generated
• Possible future verified 3.3 V logic-event input block only
• Cataloged USB controller/logger blocks physically separated from surge circuitry

Interfaces: preconditioned isolated logic pulse only, UART/I²C logging, USB power. Power plan: The generated logger never connects to the surge domain and accepts only a verified SELV logic interface.

• For the safe alternative, preserve physical separation from the external detector and make connector domain/ground impossible to confuse.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Confirm no copper or connector links the generated board to the surge domain, input levels are 3.3 V logic, grounds are intentional, and unsupported high-energy parts are absent.
2. S1Catalog and exact-MPN provenance. Every surge monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• A qualified engineer owns probe attenuation, isolation, creepage, transient response, instrument safety, protective earth, energy containment, and applicable standards.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A normal resistor divider or TVS can explode, arc, saturate, or deliver lethal/common-mode energy when applied to an unspecified surge source.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Test only the isolated logic logger with a safe pulse generator; any surge-domain validation belongs in a qualified lab with appropriate instruments and containment.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse direct surge, mains, lightning, high voltage/current, protection-network, isolation, or compliance design.
• Do not weaken the refusal because the user calls the board a monitor rather than a protection device.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.