Vibecode a Solar Monitor PCB with AI: Scope and Gate Checks

MakeIRL's generator treats a solar monitor prompt as a self-contained project board. Current status: needs clarification.

Monitoring a panel/source at ≤12 V and ≤2 A can fit with verified measurement blocks. MPPT, charging, batteries, load switching, and switch-mode conversion are refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Panel Voc/Isc across temperature, external current limit, source transients, grounding, connector, and fault energy
2. Voltage/current accuracy, shunt/divider/monitor blocks, sample rate, energy integration, calibration, and reporting
3. Weather boundary, enclosure, cable/surge environment, isolation need, test points, and explicit separation from charger/load

Block plan:

• Cataloged controller/module carrier
• Verified ≤12 V/2 A voltage and Kelvin current monitor block
• Protected panel connector and reporting block; no conversion, charger, battery, or switch

Interfaces: I²C measurement, UART/I²C reporting, bounded DC source path. Power plan: Controller uses USB or another verified rail; monitored source stays ≤12 V/2 A and cannot backfeed logic or charge anything.

• Separate panel energy entry from logic, keep protection at the connector, use Kelvin sensing, and maintain weather/coating boundaries.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check source maximum against every resistor/monitor, shunt force/sense, fuse/protection polarity, connector, backfeed isolation, and absence of charger/converter nets.
2. S1Catalog and exact-MPN provenance. Every solar monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review panel cold Voc, lightning/surge environment, outdoor ingress, cable grounding, measurement error, fault energy, and safe disconnection.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A panel labeled 12 V can exceed that open-circuit in cold sun, and a monitor connected incorrectly can backfeed a dark panel or attached system.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep a current-limited source across allowed voltage/current and dynamic profiles, compare energy readings, test backfeed/disconnect, temperature, and enclosure leakage.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse MPPT, charging, batteries, converters, load switching, panels beyond 12 V/2 A, or outdoor surge guarantees.
• The generated alternative is measurement-only and cannot be represented as a solar charge controller.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.