Vibecode a Power Distribution Monitor: AI Scope Limits Guide

MakeIRL's generator treats a power distribution monitor prompt as a self-contained project board. Current status: needs clarification.

A measurement-only path under 12 V/2 A can fit after verified sensing blocks. Distribution above 2 A, load switching, multiple protected branches, or fault-energy control is refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Source and branch voltage/current/transients, external fuse, conductor and connector, fault energy, number of branches, and grounding
2. Per-branch sensing and accuracy, shunts, alerts, sample rates, isolation, backfeed, logging, and safe state
3. Copper/thermal environment, enclosure, wire torque, service/disconnect, test load, and explicit prohibited loads

Block plan:

• Cataloged controller/module carrier
• Verified single-branch ≤12 V/2 A Kelvin monitor block
• Verified keyed connector/protection block; no distributor, switch, fuse coordination, or high-current bus

Interfaces: I²C current/voltage measurement, UART/I²C reporting, one bounded DC force path. Power plan: One externally protected branch at ≤12 V/2 A; logic power must not backfeed the branch.

• Use broad symmetric force copper and Kelvin sense, keep USB/logic grounds deliberate, and support terminals against wire torque.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check input/output polarity, current path and necks, shunt force/sense, fuse ownership, connector rating, backfeed, thermal assumptions, and the absence of switches.
2. S1Catalog and exact-MPN provenance. Every power distribution monitor block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review fault current, fuse/selectivity, connector and wire rating, shunt heat, enclosure, service arcs, grounding, branch failure, and claims.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A 2 A sensor IC does not make copper, vias, terminals, fuses, wiring, or fault interruption safe for a larger distribution system.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Sweep the one allowed branch to 2 A, map voltage drop/heat and accuracy, test disconnect/backfeed, and inspect terminal behavior under rated wire torque.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse above 12 V/2 A, multi-branch distribution, batteries, motors, heaters, load switching, fuse coordination, or high-energy fault design.
• Offer one bounded monitor channel rather than pretending the generator supports a power distribution unit.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.