Vibecode a Relay Controller PCB with AI: Limits and Gates

MakeIRL's generator treats a relay controller prompt as a self-contained project board. Current status: needs clarification.

A small SELV coil driver could fit after verified relay/driver blocks exist, but mains, motors, heaters, high-energy contacts, and safety control are refused.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Relay MPN, coil voltage/current and tolerance, driver, flyback behavior, contact form, load voltage/current/inrush/type, and cycle target
2. Safe/default state, isolation and grounding, fuse/snubber need, connector, wire size, spacing, firmware, and feedback
3. Enclosure, terminal wire/tool access, mechanical support, thermal ambient, test load, and prohibited uses

Block plan:

• Cataloged controller/module carrier
• Verified transistor/relay/flyback block with exact coil and contact limits
• Verified SELV input and keyed contact terminal blocks; no hazardous load block

Interfaces: GPIO coil control, optional contact-state feedback, SELV relay contacts. Power plan: Coils and contacts stay within 12 V SELV and 2 A board envelope; no mains, motors, heaters, or generated high-energy protection.

• Separate coil/control and contact copper, keep flyback local, give terminals broad paths and mechanical space, and preserve spacing between domains.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Check relay coil/contact pin map, driver rating and base/gate network, flyback polarity, safe pull state, terminal view, contact copper, and prohibited domain spacing.
2. S1Catalog and exact-MPN provenance. Every relay controller block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review contact inrush and load type, relay life/derating, fault energy, default state, firmware failure, fusing, spacing, terminal torque, and product safety.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A relay rated for a resistive load can weld on motor, lamp, or capacitive inrush, and a missing pulldown can energize it during reset.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Cycle each relay with the allowed representative load, test reset/power loss, monitor driver and terminal heat, inspect flyback, and verify isolation between open contacts.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse mains, motors, heaters, safety interlocks, inductive/high-inrush loads, or contact ratings outside 12 V/2 A.
• Do not market an SELV relay board as a general appliance or industrial power controller.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.