Vibecode an NFC Tag Reader PCB with AI: RF Limits Guide

MakeIRL's generator treats a NFC tag reader prompt as a self-contained project board. Current status: refused.

NFC is RF. The current deterministic policy refuses reader IC matching, loop antenna, field power, and unknown modules. A future verified complete module carrier could be reconsidered.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact reader/module, integrated or external antenna, frequency, matching/reference layout, tag distance/orientation, metal/enclosure, and certification context
2. Host interface and voltage, IRQ/reset, current peaks, USB or other power, ESD, firmware/library, and secure-element requirements
3. Antenna outline/keepout, board edge, user touch zone, connector, mounting, shielding, test tags, and acceptance range

Block plan:

• No reader IC, matching network, antenna coil, or RF layout is generated
• Possible future verified complete NFC-module carrier block
• Cataloged USB power and low-speed host blocks only after RF module policy permits

Interfaces: future I²C/SPI/UART module host, interrupt/reset GPIO, USB power. Power plan: Only low-voltage module power could fit; RF field generation and any boost/load modulation circuit stay out of scope.

• A future carrier must preserve the module antenna keepout, avoid metal/battery beneath it, and keep connector/ESD currents away from RF ground.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Current gate should produce a refusal. A future module path must verify exact module, host pins/voltage, keepout, power peaks, ESD, and no custom RF copper.
2. S1Catalog and exact-MPN provenance. Every NFC tag reader block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review RF exposure/compliance, antenna tuning, enclosure and metal detuning, secure transactions, tag population, firmware, ESD, and privacy/security.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• An NFC schematic can be electrically connected while the loop, matching, ground, and enclosure make read range negligible or unstable.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Future verified hardware needs read/write tests across tags, orientations, distance, metal/enclosure, supply corners, coexistence, ESD, and compliance evidence.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse reader IC integration, antenna layout, matching, RF power, unknown modules, or range claims.
• Do not bypass RF refusal by calling an NFC antenna a connector or a slow SPI peripheral.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.