Vibecode a GNSS Logger PCB with AI: RF Refusal Design Guide

MakeIRL's generator treats a GNSS logger prompt as a self-contained project board. Current status: refused.

GNSS is RF and current policy refuses it. A future verified complete receiver-module block could pair with verified storage, but antenna and battery claims would still need physical evidence.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact GNSS module, constellations/bands, integrated/external antenna, LNA/bias, reference layout, timing, sensitivity, and certification
2. UART/I²C/SPI protocol, update, storage capacity/endurance, timestamp/data format, power-fail recovery, firmware, and export
3. Peak/backup current, USB or battery, enclosure/sky view, antenna keepout, connector, mounting, EMI sources, and test plan

Block plan:

• No GNSS/RF/antenna block under current policy
• Future verified complete receiver-module block with fixed antenna/reference constraints
• Future verified storage/RTC and USB power blocks; battery remains separately refused

Interfaces: future UART receiver data, slow SPI storage, timing GPIO. Power plan: Future safe variant is USB powered; active-antenna bias must be part of a verified module block and battery/charging is excluded.

• A future design must preserve antenna view/keepout and RF return, isolate switching noise, and place storage/current bursts away from the receiver supply.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Current gate returns refusal. Future checks require exact module/antenna, host pins, bias protection, storage/RTC nets, power peaks, keepout, and no battery.
2. S1Catalog and exact-MPN provenance. Every GNSS logger block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review antenna and enclosure, LNA/bias faults, certification, RF coexistence, timing accuracy, storage integrity, privacy, battery policy, and field conditions.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A module emitting NMEA on a bench can still have poor cold-start or sensitivity once enclosed near a display, battery, cable, or noisy converter.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Future hardware needs cold/warm acquisition, carrier-to-noise and timing tests, enclosure antenna performance, storage power-fail endurance, current profiling, ESD, and field logs.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse GNSS/RF, antenna, LNA matching, active-antenna power, batteries, and location-performance claims today.
• Do not treat UART output from a hypothetical module as evidence that the RF portion is supported.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.